1#include <dt-bindings/clock/tegra30-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra30-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7#include "skeleton.dtsi" 8 9/ { 10 compatible = "nvidia,tegra30"; 11 interrupt-parent = <&lic>; 12 13 pcie@3000 { 14 compatible = "nvidia,tegra30-pcie"; 15 device_type = "pci"; 16 reg = <0x00003000 0x00000800 /* PADS registers */ 17 0x00003800 0x00000200 /* AFI registers */ 18 0x10000000 0x10000000>; /* configuration space */ 19 reg-names = "pads", "afi", "cs"; 20 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 21 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22 interrupt-names = "intr", "msi"; 23 24 #interrupt-cells = <1>; 25 interrupt-map-mask = <0 0 0 0>; 26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 27 28 bus-range = <0x00 0xff>; 29 #address-cells = <3>; 30 #size-cells = <2>; 31 32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ 33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ 35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ 36 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ 37 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 38 39 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 40 <&tegra_car TEGRA30_CLK_AFI>, 41 <&tegra_car TEGRA30_CLK_PLL_E>, 42 <&tegra_car TEGRA30_CLK_CML0>; 43 clock-names = "pex", "afi", "pll_e", "cml"; 44 resets = <&tegra_car 70>, 45 <&tegra_car 72>, 46 <&tegra_car 74>; 47 reset-names = "pex", "afi", "pcie_x"; 48 status = "disabled"; 49 50 pci@1,0 { 51 device_type = "pci"; 52 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; 53 reg = <0x000800 0 0 0 0>; 54 status = "disabled"; 55 56 #address-cells = <3>; 57 #size-cells = <2>; 58 ranges; 59 60 nvidia,num-lanes = <2>; 61 }; 62 63 pci@2,0 { 64 device_type = "pci"; 65 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; 66 reg = <0x001000 0 0 0 0>; 67 status = "disabled"; 68 69 #address-cells = <3>; 70 #size-cells = <2>; 71 ranges; 72 73 nvidia,num-lanes = <2>; 74 }; 75 76 pci@3,0 { 77 device_type = "pci"; 78 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; 79 reg = <0x001800 0 0 0 0>; 80 status = "disabled"; 81 82 #address-cells = <3>; 83 #size-cells = <2>; 84 ranges; 85 86 nvidia,num-lanes = <2>; 87 }; 88 }; 89 90 host1x@50000000 { 91 compatible = "nvidia,tegra30-host1x", "simple-bus"; 92 reg = <0x50000000 0x00024000>; 93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 94 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 95 clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 96 resets = <&tegra_car 28>; 97 reset-names = "host1x"; 98 99 #address-cells = <1>; 100 #size-cells = <1>; 101 102 ranges = <0x54000000 0x54000000 0x04000000>; 103 104 mpe@54040000 { 105 compatible = "nvidia,tegra30-mpe"; 106 reg = <0x54040000 0x00040000>; 107 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&tegra_car TEGRA30_CLK_MPE>; 109 resets = <&tegra_car 60>; 110 reset-names = "mpe"; 111 }; 112 113 vi@54080000 { 114 compatible = "nvidia,tegra30-vi"; 115 reg = <0x54080000 0x00040000>; 116 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&tegra_car TEGRA30_CLK_VI>; 118 resets = <&tegra_car 20>; 119 reset-names = "vi"; 120 }; 121 122 epp@540c0000 { 123 compatible = "nvidia,tegra30-epp"; 124 reg = <0x540c0000 0x00040000>; 125 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&tegra_car TEGRA30_CLK_EPP>; 127 resets = <&tegra_car 19>; 128 reset-names = "epp"; 129 }; 130 131 isp@54100000 { 132 compatible = "nvidia,tegra30-isp"; 133 reg = <0x54100000 0x00040000>; 134 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&tegra_car TEGRA30_CLK_ISP>; 136 resets = <&tegra_car 23>; 137 reset-names = "isp"; 138 }; 139 140 gr2d@54140000 { 141 compatible = "nvidia,tegra30-gr2d"; 142 reg = <0x54140000 0x00040000>; 143 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 145 resets = <&tegra_car 21>; 146 reset-names = "2d"; 147 }; 148 149 gr3d@54180000 { 150 compatible = "nvidia,tegra30-gr3d"; 151 reg = <0x54180000 0x00040000>; 152 clocks = <&tegra_car TEGRA30_CLK_GR3D 153 &tegra_car TEGRA30_CLK_GR3D2>; 154 clock-names = "3d", "3d2"; 155 resets = <&tegra_car 24>, 156 <&tegra_car 98>; 157 reset-names = "3d", "3d2"; 158 }; 159 160 dc@54200000 { 161 compatible = "nvidia,tegra30-dc"; 162 reg = <0x54200000 0x00040000>; 163 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 165 <&tegra_car TEGRA30_CLK_PLL_P>; 166 clock-names = "dc", "parent"; 167 resets = <&tegra_car 27>; 168 reset-names = "dc"; 169 170 iommus = <&mc TEGRA_SWGROUP_DC>; 171 172 nvidia,head = <0>; 173 174 rgb { 175 status = "disabled"; 176 }; 177 }; 178 179 dc@54240000 { 180 compatible = "nvidia,tegra30-dc"; 181 reg = <0x54240000 0x00040000>; 182 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&tegra_car TEGRA30_CLK_DISP2>, 184 <&tegra_car TEGRA30_CLK_PLL_P>; 185 clock-names = "dc", "parent"; 186 resets = <&tegra_car 26>; 187 reset-names = "dc"; 188 189 iommus = <&mc TEGRA_SWGROUP_DCB>; 190 191 nvidia,head = <1>; 192 193 rgb { 194 status = "disabled"; 195 }; 196 }; 197 198 hdmi@54280000 { 199 compatible = "nvidia,tegra30-hdmi"; 200 reg = <0x54280000 0x00040000>; 201 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&tegra_car TEGRA30_CLK_HDMI>, 203 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 204 clock-names = "hdmi", "parent"; 205 resets = <&tegra_car 51>; 206 reset-names = "hdmi"; 207 status = "disabled"; 208 }; 209 210 tvo@542c0000 { 211 compatible = "nvidia,tegra30-tvo"; 212 reg = <0x542c0000 0x00040000>; 213 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&tegra_car TEGRA30_CLK_TVO>; 215 status = "disabled"; 216 }; 217 218 dsi@54300000 { 219 compatible = "nvidia,tegra30-dsi"; 220 reg = <0x54300000 0x00040000>; 221 clocks = <&tegra_car TEGRA30_CLK_DSIA>, 222 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 223 clock-names = "dsi", "parent"; 224 resets = <&tegra_car 48>; 225 reset-names = "dsi"; 226 status = "disabled"; 227 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 dsi@54400000 { 233 compatible = "nvidia,tegra30-dsi"; 234 reg = <0x54400000 0x00040000>; 235 clocks = <&tegra_car TEGRA30_CLK_DSIB>, 236 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 237 clock-names = "dsi", "parent"; 238 resets = <&tegra_car 84>; 239 reset-names = "dsi"; 240 status = "disabled"; 241 242 #address-cells = <1>; 243 #size-cells = <0>; 244 }; 245 }; 246 247 timer@50040600 { 248 compatible = "arm,cortex-a9-twd-timer"; 249 reg = <0x50040600 0x20>; 250 interrupt-parent = <&intc>; 251 interrupts = <GIC_PPI 13 252 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 253 clocks = <&tegra_car TEGRA30_CLK_TWD>; 254 }; 255 256 intc: interrupt-controller@50041000 { 257 compatible = "arm,cortex-a9-gic"; 258 reg = <0x50041000 0x1000 259 0x50040100 0x0100>; 260 interrupt-controller; 261 #interrupt-cells = <3>; 262 interrupt-parent = <&intc>; 263 }; 264 265 cache-controller@50043000 { 266 compatible = "arm,pl310-cache"; 267 reg = <0x50043000 0x1000>; 268 arm,data-latency = <6 6 2>; 269 arm,tag-latency = <5 5 2>; 270 cache-unified; 271 cache-level = <2>; 272 }; 273 274 lic: interrupt-controller@60004000 { 275 compatible = "nvidia,tegra30-ictlr"; 276 reg = <0x60004000 0x100>, 277 <0x60004100 0x50>, 278 <0x60004200 0x50>, 279 <0x60004300 0x50>, 280 <0x60004400 0x50>; 281 interrupt-controller; 282 #interrupt-cells = <3>; 283 interrupt-parent = <&intc>; 284 }; 285 286 timer@60005000 { 287 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 288 reg = <0x60005000 0x400>; 289 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 296 }; 297 298 tegra_car: clock@60006000 { 299 compatible = "nvidia,tegra30-car"; 300 reg = <0x60006000 0x1000>; 301 #clock-cells = <1>; 302 #reset-cells = <1>; 303 }; 304 305 flow-controller@60007000 { 306 compatible = "nvidia,tegra30-flowctrl"; 307 reg = <0x60007000 0x1000>; 308 }; 309 310 apbdma: dma@6000a000 { 311 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 312 reg = <0x6000a000 0x1400>; 313 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 346 resets = <&tegra_car 34>; 347 reset-names = "dma"; 348 #dma-cells = <1>; 349 }; 350 351 ahb: ahb@6000c000 { 352 compatible = "nvidia,tegra30-ahb"; 353 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ 354 }; 355 356 gpio: gpio@6000d000 { 357 compatible = "nvidia,tegra30-gpio"; 358 reg = <0x6000d000 0x1000>; 359 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 367 #gpio-cells = <2>; 368 gpio-controller; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 /* 372 gpio-ranges = <&pinmux 0 0 248>; 373 */ 374 }; 375 376 /* Audio Bitstream Engine */ 377 bsea@60011000 { 378 compatible = "nvidia,tegra30-bsea"; 379 reg = <0x60011000 0x1000>, <0x4000c000 0x4000>; 380 reg-names = "bsea", "iram-buffer"; 381 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 382 interrupt-names = "bsea"; 383 clocks = <&tegra_car TEGRA30_CLK_BSEA>; 384 resets = <&tegra_car 62>; 385 reset-names = "bsea"; 386 status = "disabled"; 387 }; 388 389 /* Video Bitstream Engine */ 390 bsev@6001b000 { 391 compatible = "nvidia,tegra30-bsev"; 392 reg = <0x6001b000 0x1000>, <0x40008000 0x4000>; 393 reg-names = "bsev", "iram-buffer"; 394 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 395 interrupt-names = "bsev"; 396 clocks = <&tegra_car TEGRA30_CLK_BSEV>, 397 <&tegra_car TEGRA30_CLK_VDE>; 398 clock-names = "bsev", "vde"; 399 resets = <&tegra_car 63>, 400 <&tegra_car 61>; 401 reset-names = "bsev", "vde"; 402 status = "disabled"; 403 }; 404 405 apbmisc@70000800 { 406 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; 407 reg = <0x70000800 0x64 /* Chip revision */ 408 0x70000008 0x04>; /* Strapping options */ 409 }; 410 411 pinmux: pinmux@70000868 { 412 compatible = "nvidia,tegra30-pinmux"; 413 reg = <0x70000868 0xd4 /* Pad control registers */ 414 0x70003000 0x3e4>; /* Mux registers */ 415 }; 416 417 /* 418 * There are two serial driver i.e. 8250 based simple serial 419 * driver and APB DMA based serial driver for higher baudrate 420 * and performace. To enable the 8250 based driver, the compatible 421 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable 422 * the APB DMA based serial driver, the compatible is 423 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". 424 */ 425 uarta: serial@70006000 { 426 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 427 reg = <0x70006000 0x40>; 428 reg-shift = <2>; 429 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 431 resets = <&tegra_car 6>; 432 reset-names = "serial"; 433 dmas = <&apbdma 8>, <&apbdma 8>; 434 dma-names = "rx", "tx"; 435 status = "disabled"; 436 }; 437 438 uartb: serial@70006040 { 439 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 440 reg = <0x70006040 0x40>; 441 reg-shift = <2>; 442 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 444 resets = <&tegra_car 7>; 445 reset-names = "serial"; 446 dmas = <&apbdma 9>, <&apbdma 9>; 447 dma-names = "rx", "tx"; 448 status = "disabled"; 449 }; 450 451 uartc: serial@70006200 { 452 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 453 reg = <0x70006200 0x100>; 454 reg-shift = <2>; 455 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 457 resets = <&tegra_car 55>; 458 reset-names = "serial"; 459 dmas = <&apbdma 10>, <&apbdma 10>; 460 dma-names = "rx", "tx"; 461 status = "disabled"; 462 }; 463 464 uartd: serial@70006300 { 465 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 466 reg = <0x70006300 0x100>; 467 reg-shift = <2>; 468 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 470 resets = <&tegra_car 65>; 471 reset-names = "serial"; 472 dmas = <&apbdma 19>, <&apbdma 19>; 473 dma-names = "rx", "tx"; 474 status = "disabled"; 475 }; 476 477 uarte: serial@70006400 { 478 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 479 reg = <0x70006400 0x100>; 480 reg-shift = <2>; 481 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 483 resets = <&tegra_car 66>; 484 reset-names = "serial"; 485 dmas = <&apbdma 20>, <&apbdma 20>; 486 dma-names = "rx", "tx"; 487 status = "disabled"; 488 }; 489 490 pwm: pwm@7000a000 { 491 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 492 reg = <0x7000a000 0x100>; 493 #pwm-cells = <2>; 494 clocks = <&tegra_car TEGRA30_CLK_PWM>; 495 resets = <&tegra_car 17>; 496 reset-names = "pwm"; 497 status = "disabled"; 498 }; 499 500 rtc@7000e000 { 501 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 502 reg = <0x7000e000 0x100>; 503 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&tegra_car TEGRA30_CLK_RTC>; 505 }; 506 507 i2c@7000c000 { 508 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 509 reg = <0x7000c000 0x100>; 510 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 clocks = <&tegra_car TEGRA30_CLK_I2C1>, 514 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 515 clock-names = "div-clk", "fast-clk"; 516 resets = <&tegra_car 12>; 517 reset-names = "i2c"; 518 dmas = <&apbdma 21>, <&apbdma 21>; 519 dma-names = "rx", "tx"; 520 status = "disabled"; 521 }; 522 523 i2c@7000c400 { 524 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 525 reg = <0x7000c400 0x100>; 526 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 clocks = <&tegra_car TEGRA30_CLK_I2C2>, 530 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 531 clock-names = "div-clk", "fast-clk"; 532 resets = <&tegra_car 54>; 533 reset-names = "i2c"; 534 dmas = <&apbdma 22>, <&apbdma 22>; 535 dma-names = "rx", "tx"; 536 status = "disabled"; 537 }; 538 539 i2c@7000c500 { 540 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 541 reg = <0x7000c500 0x100>; 542 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 clocks = <&tegra_car TEGRA30_CLK_I2C3>, 546 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 547 clock-names = "div-clk", "fast-clk"; 548 resets = <&tegra_car 67>; 549 reset-names = "i2c"; 550 dmas = <&apbdma 23>, <&apbdma 23>; 551 dma-names = "rx", "tx"; 552 status = "disabled"; 553 }; 554 555 i2c@7000c700 { 556 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 557 reg = <0x7000c700 0x100>; 558 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clocks = <&tegra_car TEGRA30_CLK_I2C4>, 562 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 563 resets = <&tegra_car 103>; 564 reset-names = "i2c"; 565 clock-names = "div-clk", "fast-clk"; 566 dmas = <&apbdma 26>, <&apbdma 26>; 567 dma-names = "rx", "tx"; 568 status = "disabled"; 569 }; 570 571 i2c@7000d000 { 572 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 573 reg = <0x7000d000 0x100>; 574 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 clocks = <&tegra_car TEGRA30_CLK_I2C5>, 578 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 579 clock-names = "div-clk", "fast-clk"; 580 resets = <&tegra_car 47>; 581 reset-names = "i2c"; 582 dmas = <&apbdma 24>, <&apbdma 24>; 583 dma-names = "rx", "tx"; 584 status = "disabled"; 585 }; 586 587 spi@7000d400 { 588 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 589 reg = <0x7000d400 0x200>; 590 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 594 resets = <&tegra_car 41>; 595 reset-names = "spi"; 596 dmas = <&apbdma 15>, <&apbdma 15>; 597 dma-names = "rx", "tx"; 598 status = "disabled"; 599 }; 600 601 spi@7000d600 { 602 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 603 reg = <0x7000d600 0x200>; 604 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 608 resets = <&tegra_car 44>; 609 reset-names = "spi"; 610 dmas = <&apbdma 16>, <&apbdma 16>; 611 dma-names = "rx", "tx"; 612 status = "disabled"; 613 }; 614 615 spi@7000d800 { 616 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 617 reg = <0x7000d800 0x200>; 618 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 622 resets = <&tegra_car 46>; 623 reset-names = "spi"; 624 dmas = <&apbdma 17>, <&apbdma 17>; 625 dma-names = "rx", "tx"; 626 status = "disabled"; 627 }; 628 629 spi@7000da00 { 630 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 631 reg = <0x7000da00 0x200>; 632 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 636 resets = <&tegra_car 68>; 637 reset-names = "spi"; 638 dmas = <&apbdma 18>, <&apbdma 18>; 639 dma-names = "rx", "tx"; 640 status = "disabled"; 641 }; 642 643 spi@7000dc00 { 644 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 645 reg = <0x7000dc00 0x200>; 646 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 650 resets = <&tegra_car 104>; 651 reset-names = "spi"; 652 dmas = <&apbdma 27>, <&apbdma 27>; 653 dma-names = "rx", "tx"; 654 status = "disabled"; 655 }; 656 657 spi@7000de00 { 658 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 659 reg = <0x7000de00 0x200>; 660 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 664 resets = <&tegra_car 106>; 665 reset-names = "spi"; 666 dmas = <&apbdma 28>, <&apbdma 28>; 667 dma-names = "rx", "tx"; 668 status = "disabled"; 669 }; 670 671 kbc@7000e200 { 672 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 673 reg = <0x7000e200 0x100>; 674 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&tegra_car TEGRA30_CLK_KBC>; 676 resets = <&tegra_car 36>; 677 reset-names = "kbc"; 678 status = "disabled"; 679 }; 680 681 pmc@7000e400 { 682 compatible = "nvidia,tegra30-pmc"; 683 reg = <0x7000e400 0x400>; 684 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 685 clock-names = "pclk", "clk32k_in"; 686 }; 687 688 mc: memory-controller@7000f000 { 689 compatible = "nvidia,tegra30-mc"; 690 reg = <0x7000f000 0x400>; 691 clocks = <&tegra_car TEGRA30_CLK_MC>; 692 clock-names = "mc"; 693 694 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 695 696 #iommu-cells = <1>; 697 }; 698 699 fuse@7000f800 { 700 compatible = "nvidia,tegra30-efuse"; 701 reg = <0x7000f800 0x400>; 702 clocks = <&tegra_car TEGRA30_CLK_FUSE>; 703 clock-names = "fuse"; 704 resets = <&tegra_car 39>; 705 reset-names = "fuse"; 706 }; 707 708 hda@70030000 { 709 compatible = "nvidia,tegra30-hda"; 710 reg = <0x70030000 0x10000>; 711 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&tegra_car TEGRA30_CLK_HDA>, 713 <&tegra_car TEGRA30_CLK_HDA2HDMI>, 714 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; 715 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 716 resets = <&tegra_car 125>, /* hda */ 717 <&tegra_car 128>, /* hda2hdmi */ 718 <&tegra_car 111>; /* hda2codec_2x */ 719 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 720 status = "disabled"; 721 }; 722 723 ahub@70080000 { 724 compatible = "nvidia,tegra30-ahub"; 725 reg = <0x70080000 0x200 726 0x70080200 0x100>; 727 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 729 <&tegra_car TEGRA30_CLK_APBIF>; 730 clock-names = "d_audio", "apbif"; 731 resets = <&tegra_car 106>, /* d_audio */ 732 <&tegra_car 107>, /* apbif */ 733 <&tegra_car 30>, /* i2s0 */ 734 <&tegra_car 11>, /* i2s1 */ 735 <&tegra_car 18>, /* i2s2 */ 736 <&tegra_car 101>, /* i2s3 */ 737 <&tegra_car 102>, /* i2s4 */ 738 <&tegra_car 108>, /* dam0 */ 739 <&tegra_car 109>, /* dam1 */ 740 <&tegra_car 110>, /* dam2 */ 741 <&tegra_car 10>; /* spdif */ 742 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 743 "i2s3", "i2s4", "dam0", "dam1", "dam2", 744 "spdif"; 745 dmas = <&apbdma 1>, <&apbdma 1>, 746 <&apbdma 2>, <&apbdma 2>, 747 <&apbdma 3>, <&apbdma 3>, 748 <&apbdma 4>, <&apbdma 4>; 749 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 750 "rx3", "tx3"; 751 ranges; 752 #address-cells = <1>; 753 #size-cells = <1>; 754 755 tegra_i2s0: i2s@70080300 { 756 compatible = "nvidia,tegra30-i2s"; 757 reg = <0x70080300 0x100>; 758 nvidia,ahub-cif-ids = <4 4>; 759 clocks = <&tegra_car TEGRA30_CLK_I2S0>; 760 resets = <&tegra_car 30>; 761 reset-names = "i2s"; 762 status = "disabled"; 763 }; 764 765 tegra_i2s1: i2s@70080400 { 766 compatible = "nvidia,tegra30-i2s"; 767 reg = <0x70080400 0x100>; 768 nvidia,ahub-cif-ids = <5 5>; 769 clocks = <&tegra_car TEGRA30_CLK_I2S1>; 770 resets = <&tegra_car 11>; 771 reset-names = "i2s"; 772 status = "disabled"; 773 }; 774 775 tegra_i2s2: i2s@70080500 { 776 compatible = "nvidia,tegra30-i2s"; 777 reg = <0x70080500 0x100>; 778 nvidia,ahub-cif-ids = <6 6>; 779 clocks = <&tegra_car TEGRA30_CLK_I2S2>; 780 resets = <&tegra_car 18>; 781 reset-names = "i2s"; 782 status = "disabled"; 783 }; 784 785 tegra_i2s3: i2s@70080600 { 786 compatible = "nvidia,tegra30-i2s"; 787 reg = <0x70080600 0x100>; 788 nvidia,ahub-cif-ids = <7 7>; 789 clocks = <&tegra_car TEGRA30_CLK_I2S3>; 790 resets = <&tegra_car 101>; 791 reset-names = "i2s"; 792 status = "disabled"; 793 }; 794 795 tegra_i2s4: i2s@70080700 { 796 compatible = "nvidia,tegra30-i2s"; 797 reg = <0x70080700 0x100>; 798 nvidia,ahub-cif-ids = <8 8>; 799 clocks = <&tegra_car TEGRA30_CLK_I2S4>; 800 resets = <&tegra_car 102>; 801 reset-names = "i2s"; 802 status = "disabled"; 803 }; 804 }; 805 806 sdhci@78000000 { 807 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 808 reg = <0x78000000 0x200>; 809 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 811 resets = <&tegra_car 14>; 812 reset-names = "sdhci"; 813 status = "disabled"; 814 }; 815 816 sdhci@78000200 { 817 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 818 reg = <0x78000200 0x200>; 819 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 821 resets = <&tegra_car 9>; 822 reset-names = "sdhci"; 823 status = "disabled"; 824 }; 825 826 sdhci@78000400 { 827 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 828 reg = <0x78000400 0x200>; 829 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 831 resets = <&tegra_car 69>; 832 reset-names = "sdhci"; 833 status = "disabled"; 834 }; 835 836 sdhci@78000600 { 837 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 838 reg = <0x78000600 0x200>; 839 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 841 resets = <&tegra_car 15>; 842 reset-names = "sdhci"; 843 status = "disabled"; 844 }; 845 846 usb@7d000000 { 847 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 848 reg = <0x7d000000 0x4000>; 849 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 850 phy_type = "utmi"; 851 clocks = <&tegra_car TEGRA30_CLK_USBD>; 852 resets = <&tegra_car 22>; 853 reset-names = "usb"; 854 nvidia,needs-double-reset; 855 nvidia,phy = <&phy1>; 856 status = "disabled"; 857 }; 858 859 phy1: usb-phy@7d000000 { 860 compatible = "nvidia,tegra30-usb-phy"; 861 reg = <0x7d000000 0x4000 0x7d000000 0x4000>; 862 phy_type = "utmi"; 863 clocks = <&tegra_car TEGRA30_CLK_USBD>, 864 <&tegra_car TEGRA30_CLK_PLL_U>, 865 <&tegra_car TEGRA30_CLK_USBD>; 866 clock-names = "reg", "pll_u", "utmi-pads"; 867 resets = <&tegra_car 22>, <&tegra_car 22>; 868 reset-names = "usb", "utmi-pads"; 869 nvidia,hssync-start-delay = <9>; 870 nvidia,idle-wait-delay = <17>; 871 nvidia,elastic-limit = <16>; 872 nvidia,term-range-adj = <6>; 873 nvidia,xcvr-setup = <51>; 874 nvidia.xcvr-setup-use-fuses; 875 nvidia,xcvr-lsfslew = <1>; 876 nvidia,xcvr-lsrslew = <1>; 877 nvidia,xcvr-hsslew = <32>; 878 nvidia,hssquelch-level = <2>; 879 nvidia,hsdiscon-level = <5>; 880 nvidia,has-utmi-pad-registers; 881 status = "disabled"; 882 }; 883 884 usb@7d004000 { 885 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 886 reg = <0x7d004000 0x4000>; 887 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 888 phy_type = "utmi"; 889 clocks = <&tegra_car TEGRA30_CLK_USB2>; 890 resets = <&tegra_car 58>; 891 reset-names = "usb"; 892 nvidia,phy = <&phy2>; 893 status = "disabled"; 894 }; 895 896 phy2: usb-phy@7d004000 { 897 compatible = "nvidia,tegra30-usb-phy"; 898 reg = <0x7d004000 0x4000 0x7d000000 0x4000>; 899 phy_type = "utmi"; 900 clocks = <&tegra_car TEGRA30_CLK_USB2>, 901 <&tegra_car TEGRA30_CLK_PLL_U>, 902 <&tegra_car TEGRA30_CLK_USBD>; 903 clock-names = "reg", "pll_u", "utmi-pads"; 904 resets = <&tegra_car 58>, <&tegra_car 22>; 905 reset-names = "usb", "utmi-pads"; 906 nvidia,hssync-start-delay = <9>; 907 nvidia,idle-wait-delay = <17>; 908 nvidia,elastic-limit = <16>; 909 nvidia,term-range-adj = <6>; 910 nvidia,xcvr-setup = <51>; 911 nvidia.xcvr-setup-use-fuses; 912 nvidia,xcvr-lsfslew = <2>; 913 nvidia,xcvr-lsrslew = <2>; 914 nvidia,xcvr-hsslew = <32>; 915 nvidia,hssquelch-level = <2>; 916 nvidia,hsdiscon-level = <5>; 917 status = "disabled"; 918 }; 919 920 usb@7d008000 { 921 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 922 reg = <0x7d008000 0x4000>; 923 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 924 phy_type = "utmi"; 925 clocks = <&tegra_car TEGRA30_CLK_USB3>; 926 resets = <&tegra_car 59>; 927 reset-names = "usb"; 928 nvidia,phy = <&phy3>; 929 status = "disabled"; 930 }; 931 932 phy3: usb-phy@7d008000 { 933 compatible = "nvidia,tegra30-usb-phy"; 934 reg = <0x7d008000 0x4000 0x7d000000 0x4000>; 935 phy_type = "utmi"; 936 clocks = <&tegra_car TEGRA30_CLK_USB3>, 937 <&tegra_car TEGRA30_CLK_PLL_U>, 938 <&tegra_car TEGRA30_CLK_USBD>; 939 clock-names = "reg", "pll_u", "utmi-pads"; 940 resets = <&tegra_car 59>, <&tegra_car 22>; 941 reset-names = "usb", "utmi-pads"; 942 nvidia,hssync-start-delay = <0>; 943 nvidia,idle-wait-delay = <17>; 944 nvidia,elastic-limit = <16>; 945 nvidia,term-range-adj = <6>; 946 nvidia,xcvr-setup = <51>; 947 nvidia.xcvr-setup-use-fuses; 948 nvidia,xcvr-lsfslew = <2>; 949 nvidia,xcvr-lsrslew = <2>; 950 nvidia,xcvr-hsslew = <32>; 951 nvidia,hssquelch-level = <2>; 952 nvidia,hsdiscon-level = <5>; 953 status = "disabled"; 954 }; 955 956 cpus { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 cpu@0 { 961 device_type = "cpu"; 962 compatible = "arm,cortex-a9"; 963 reg = <0>; 964 }; 965 966 cpu@1 { 967 device_type = "cpu"; 968 compatible = "arm,cortex-a9"; 969 reg = <1>; 970 }; 971 972 cpu@2 { 973 device_type = "cpu"; 974 compatible = "arm,cortex-a9"; 975 reg = <2>; 976 }; 977 978 cpu@3 { 979 device_type = "cpu"; 980 compatible = "arm,cortex-a9"; 981 reg = <3>; 982 }; 983 }; 984 985 pmu { 986 compatible = "arm,cortex-a9-pmu"; 987 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 991 }; 992}; 993