1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> 4 * Copyright (C) 2025 Altera Corporation <www.altera.com> 5 * 6 */ 7 8 #ifndef _FIREWALL_H_ 9 #define _FIREWALL_H_ 10 11 #include <linux/bitops.h> 12 13 struct socfpga_firwall_l4_per { 14 u32 nand; /* 0x00 */ 15 u32 nand_data; 16 u32 _pad_0x8; 17 u32 usb0; 18 u32 usb1; /* 0x10 */ 19 u32 _pad_0x14; 20 u32 _pad_0x18; 21 u32 spim0; 22 u32 spim1; /* 0x20 */ 23 u32 spis0; 24 u32 spis1; 25 u32 emac0; 26 u32 emac1; /* 0x30 */ 27 u32 emac2; 28 u32 _pad_0x38; 29 u32 _pad_0x3c; 30 u32 sdmmc; /* 0x40 */ 31 u32 gpio0; 32 u32 gpio1; 33 u32 _pad_0x4c; 34 u32 i2c0; /* 0x50 */ 35 u32 i2c1; 36 u32 i2c2; 37 u32 i2c3; 38 u32 i2c4; /* 0x60 */ 39 u32 timer0; 40 u32 timer1; 41 u32 uart0; 42 u32 uart1; /* 0x70 */ 43 }; 44 45 struct socfpga_firwall_l4_sys { 46 u32 _pad_0x00; /* 0x00 */ 47 u32 _pad_0x04; 48 u32 dma_ecc; 49 u32 emac0rx_ecc; 50 u32 emac0tx_ecc; /* 0x10 */ 51 u32 emac1rx_ecc; 52 u32 emac1tx_ecc; 53 u32 emac2rx_ecc; 54 u32 emac2tx_ecc; /* 0x20 */ 55 u32 _pad_0x24; 56 u32 _pad_0x28; 57 u32 nand_ecc; 58 u32 nand_read_ecc; /* 0x30 */ 59 u32 nand_write_ecc; 60 u32 ocram_ecc; 61 u32 _pad_0x3c; 62 u32 sdmmc_ecc; /* 0x40 */ 63 u32 usb0_ecc; 64 u32 usb1_ecc; 65 u32 clock_manager; 66 u32 _pad_0x50; /* 0x50 */ 67 u32 io_manager; 68 u32 reset_manager; 69 u32 system_manager; 70 u32 osc0_timer; /* 0x60 */ 71 u32 osc1_timer; 72 u32 watchdog0; 73 u32 watchdog1; 74 u32 watchdog2; /* 0x70 */ 75 u32 watchdog3; 76 }; 77 78 #define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16)) 79 #define FIREWALL_BRIDGE_DISABLE_ALL (~0) 80 81 /* Cache coherency unit (CCU) registers */ 82 #define CCU_CPU0_MPRT_ADBASE_DDRREG 0x4400 83 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE0 0x45c0 84 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A 0x45e0 85 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B 0x4600 86 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C 0x4620 87 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D 0x4640 88 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E 0x4660 89 90 #define CCU_CPU0_MPRT_ADMASK_MEM_RAM0 0x4688 91 92 #define CCU_IOM_MPRT_ADBASE_MEMSPACE0 0x18560 93 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1A 0x18580 94 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1B 0x185a0 95 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1C 0x185c0 96 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1D 0x185e0 97 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1E 0x18600 98 99 #define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628 100 101 #define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520 102 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540 103 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560 104 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580 105 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0 106 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0 107 108 #define CCU_ADMASK_P_MASK BIT(0) 109 #define CCU_ADMASK_NS_MASK BIT(1) 110 111 #define CCU_ADBASE_DI_MASK BIT(4) 112 113 #define CCU_REG_ADDR(reg) \ 114 (SOCFPGA_CCU_ADDRESS + (reg)) 115 116 /* Firewall MPU DDR SCR registers */ 117 #define FW_MPU_DDR_SCR_EN 0x00 118 #define FW_MPU_DDR_SCR_EN_SET 0x04 119 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10 120 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14 121 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18 122 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c 123 124 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90 125 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94 126 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 127 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c 128 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff 129 130 /* Firewall F2SDRAM DDR SCR registers */ 131 #define FW_F2SDRAM_DDR_SCR_EN 0x00 132 #define FW_F2SDRAM_DDR_SCR_EN_SET 0x04 133 #define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE 0x10 134 #define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT 0x14 135 #define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT 0x18 136 #define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT 0x1c 137 138 #define MPUREGION0_ENABLE BIT(0) 139 #define NONMPUREGION0_ENABLE BIT(8) 140 141 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) 142 #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ 143 writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \ 144 writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg)) 145 #define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg) \ 146 writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg)) 147 #else 148 #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ 149 writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) 150 #endif 151 152 void firewall_setup(void); 153 154 #endif /* _FIREWALL_H_ */ 155