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Searched refs:CFG_SYS_FSL_ESDHC_ADDR (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-imx/
A Dspeed.c24 #if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR in get_clocks()
26 #elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR in get_clocks()
28 #elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR in get_clocks()
34 #if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR in get_clocks()
36 #elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR in get_clocks()
38 #elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR in get_clocks()
/arch/arm/include/asm/arch-ls102xa/
A Dconfig.h23 #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) macro
/arch/arm/mach-imx/mx7ulp/
A Dclock.c21 #if CFG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE in get_clocks()
23 #elif CFG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE in get_clocks()
/arch/arm/include/asm/arch-fsl-layerscape/
A Dimmap_lsch3.h32 #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) macro
33 #define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
A Dfsl_icid.h86 CFG_SYS_FSL_ESDHC_ADDR)
A Dimmap_lsch2.h21 #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) macro
/arch/arm/mach-imx/mx7/
A Dclock.c34 #if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR in get_clocks()
36 #elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR in get_clocks()

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