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Searched refs:CFG_SYS_FSL_SEC_ADDR (Results 1 – 15 of 15) sorted by relevance

/arch/arm/include/asm/arch-fsl-layerscape/
A Dfsl_icid.h122 CFG_SYS_FSL_SEC_ADDR, \
123 CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
189 CFG_SYS_FSL_SEC_ADDR, \
195 CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
200 CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
A Dimmap_lsch3.h117 #define CFG_SYS_FSL_SEC_ADDR \ macro
A Dimmap_lsch2.h180 #define CFG_SYS_FSL_SEC_ADDR \ macro
/arch/arm/include/asm/arch-imx8/
A Dimx-regs.h50 #define CFG_SYS_FSL_SEC_ADDR (0x31400000) macro
/arch/arm/include/asm/arch-ls102xa/
A Dconfig.h25 #define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) macro
/arch/arm/cpu/armv7/ls102xa/
A Dfdt.c96 sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR; in ft_cpu_setup()
/arch/arm/include/asm/arch-imx8m/
A Dimx-regs.h112 #define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ macro
115 #define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
/arch/powerpc/cpu/mpc85xx/
A Dliodn.c79 ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR; in setup_sec_liodn_base()
A Dfdt.c612 sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
A Dcpu_init.c665 ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR; in cpu_init_r()
/arch/arm/include/asm/arch-mx7ulp/
A Dimx-regs.h231 #define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ macro
234 #define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
/arch/arm/include/asm/arch-mx7/
A Dimx-regs.h218 #define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ macro
221 #define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
/arch/arm/cpu/armv8/fsl-layerscape/
A Dfdt.c643 sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR; in ft_cpu_setup()
/arch/arm/include/asm/arch-mx6/
A Dimx-regs.h242 #define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ macro
/arch/powerpc/include/asm/
A Dimmap_85xx.h2643 #define CFG_SYS_FSL_SEC_ADDR \ macro

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