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Searched refs:CLK_DIVIDER (Results 1 – 5 of 5) sorted by relevance

/arch/arm/include/asm/arch-tegra/
A Dap.h18 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) macro
/arch/arm/mach-tegra/
A Dcpu.h28 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) macro
A Dcpu.c435 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); in clock_enable_coresight()
/arch/arm/mach-tegra/tegra114/
A Dcpu.c163 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in t114_init_clocks()
/arch/arm/mach-tegra/tegra124/
A Dcpu.c208 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in tegra124_init_clocks()

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