CLK_DIV_CDREX0_VAL (reference) in projects: arch

Searched refs:CLK_DIV_CDREX0_VAL (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A D	exynos5_setup.h	`506 #define CLK_DIV_CDREX0_VAL NOT_AVAILABLE macro 770 #define CLK_DIV_CDREX0_VAL 0x30010100 macro`
A D	clock_init_exynos5.c	`910 writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); in exynos5420_system_clock_init()`

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