Searched refs:CLK_DIV_CPU0_VAL (Results 1 – 4 of 4) sorted by relevance
61 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); in system_clock_init()
510 #define CLK_DIV_CPU0_VAL NOT_AVAILABLE macro776 #define CLK_DIV_CPU0_VAL 0x01440020 macro
38 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ macro
812 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); in exynos5420_system_clock_init()
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