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Searched refs:CLK_DIV_CPU0_VAL (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init_exynos4.c61 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); in system_clock_init()
A Dexynos5_setup.h510 #define CLK_DIV_CPU0_VAL NOT_AVAILABLE macro
776 #define CLK_DIV_CPU0_VAL 0x01440020 macro
A Dexynos4_setup.h38 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ macro
A Dclock_init_exynos5.c812 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); in exynos5420_system_clock_init()

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