CLK_DIV_FSYS1_VAL (reference) in projects: arch

Searched refs:CLK_DIV_FSYS1_VAL (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-exynos/
A D	clock_init_exynos4.c	`68 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in system_clock_init()`
A D	exynos5_setup.h	`489 #define CLK_DIV_FSYS1_VAL NOT_AVAILABLE macro 753 #define CLK_DIV_FSYS1_VAL 0x04f13c4f macro`
A D	exynos4_setup.h	`190 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ macro`
A D	clock_init_exynos5.c	`941 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in exynos5420_system_clock_init()`

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