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Searched refs:CLK_DIV_FSYS3_VAL (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init_exynos4.c70 writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3); in system_clock_init()
A Dexynos4_setup.h208 #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ macro

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