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Searched refs:CLK_DIV_PERIC3_VAL (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A Dexynos5_setup.h686 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) macro
861 #define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \ macro
A Dclock_init_exynos5.c763 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); in exynos5250_system_clock_init()
954 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); in exynos5420_system_clock_init()

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