Searched refs:CLK_DIV_PERIL0_VAL (Results 1 – 2 of 2) sorted by relevance
| /arch/arm/mach-exynos/ | ||
| A D | clock_init_exynos4.c | 71 writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); in system_clock_init() |
| A D | exynos4_setup.h | 240 #define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \ macro |
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