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Searched refs:CLK_SRC_CORE0_VAL (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A Dexynos5_setup.h127 #define CLK_SRC_CORE0_VAL 0x00000000 macro
A Dclock_init_exynos5.c668 writel(CLK_SRC_CORE0_VAL, &clk->src_core0); in exynos5250_system_clock_init()

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