Home
last modified time | relevance | path

Searched refs:CLOCK_ID_DISPLAY2 (Results 1 – 10 of 10) sorted by relevance

/arch/arm/mach-tegra/
A Dclock.c365 if (parent == CLOCK_ID_DISPLAY || parent == CLOCK_ID_DISPLAY2) in clock_get_periph_rate()
475 if (parent == CLOCK_ID_DISPLAY || parent == CLOCK_ID_DISPLAY2) in clock_adjust_periph_pll_div()
709 if (clkid == CLOCK_ID_DISPLAY2) in clock_set_rate()
805 pll_rate[CLOCK_ID_DISPLAY2] = clock_get_rate(CLOCK_ID_DISPLAY2); in clock_init()
/arch/arm/include/asm/arch-tegra20/
A Dclock-tables.h35 CLOCK_ID_DISPLAY2 = CLOCK_ID_NONE, /* for compatibility */ enumerator
/arch/arm/include/asm/arch-tegra114/
A Dclock-tables.h26 CLOCK_ID_DISPLAY2, enumerator
/arch/arm/include/asm/arch-tegra30/
A Dclock-tables.h26 CLOCK_ID_DISPLAY2, enumerator
/arch/arm/include/asm/arch-tegra124/
A Dclock-tables.h27 CLOCK_ID_DISPLAY2, enumerator
/arch/arm/include/asm/arch-tegra210/
A Dclock-tables.h27 CLOCK_ID_DISPLAY2, enumerator
/arch/arm/mach-tegra/tegra114/
A Dclock.c676 return CLOCK_ID_DISPLAY2; in clk_id_to_pll_id()
784 case CLOCK_ID_DISPLAY2: in clock_get_simple_pll()
/arch/arm/mach-tegra/tegra30/
A Dclock.c660 return CLOCK_ID_DISPLAY2; in clk_id_to_pll_id()
888 case CLOCK_ID_DISPLAY2: in clock_get_simple_pll()
/arch/arm/mach-tegra/tegra124/
A Dclock.c859 return CLOCK_ID_DISPLAY2; in clk_id_to_pll_id()
1202 case CLOCK_ID_DISPLAY2: in clock_get_simple_pll()
/arch/arm/mach-tegra/tegra210/
A Dclock.c946 return CLOCK_ID_DISPLAY2; in clk_id_to_pll_id()
1284 case CLOCK_ID_DISPLAY2: in clock_get_simple_pll()

Completed in 26 milliseconds