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Searched refs:CONCONTROL_UPDATE_MODE (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/include/mach/
A Ddmc.h453 #define CONCONTROL_UPDATE_MODE (1 << 3) macro
/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c856 val |= CONCONTROL_UPDATE_MODE; in ddr3_mem_ctrl_init()
859 val |= CONCONTROL_UPDATE_MODE; in ddr3_mem_ctrl_init()

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