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Searched refs:CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET (Results 1 – 1 of 1) sorted by relevance

/arch/mips/mach-ath79/qca956x/
A Dclk.c142 #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) \ macro
252 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1)); in qca956x_pll_init()
276 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1), pll_regs + QCA956X_PLL_CLK_CTRL_REG); in qca956x_pll_init()
300 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0)); in qca956x_pll_init()

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