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Searched refs:CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK (Results 1 – 1 of 1) sorted by relevance

/arch/mips/mach-ath79/qca956x/
A Dclk.c145 #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008 macro
147 (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
249 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, in qca956x_pll_init()
297 cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, in qca956x_pll_init()

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