1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Cache operations for the cache instruction.
4 *
5 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
6 * (C) Copyright 1999 Silicon Graphics, Inc.
7 */
8 #ifndef __ASM_CACHEOPS_H
9 #define __ASM_CACHEOPS_H
10
11 #include <asm/cache.h>
12
13 #ifndef __ASSEMBLY__
14 #include <linux/types.h>
15
mips_cache(int op,const volatile void * addr)16 static inline void mips_cache(int op, const volatile void *addr)
17 {
18 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
19 __builtin_mips_cache(op, addr);
20 #else
21 __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
22 #endif
23 }
24
25 #define MIPS32_WHICH_ICACHE 0x0
26 #define MIPS32_FETCH_AND_LOCK 0x7
27
28 #define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
29
30 /* Prefetch and lock instructions into cache */
icache_lock(void * func,size_t len)31 static inline void icache_lock(void *func, size_t len)
32 {
33 int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
34
35 for (i = 0; i < lines; i++) {
36 asm volatile (" cache %0, %1(%2)"
37 : /* No Output */
38 : "I" ICACHE_LOAD_LOCK,
39 "n" (i * ARCH_DMA_MINALIGN),
40 "r" (func)
41 : /* No Clobbers */);
42 }
43 }
44 #endif /* !__ASSEMBLY__ */
45
46 /*
47 * Cache Operations available on all MIPS processors with R4000-style caches
48 */
49 #define INDEX_INVALIDATE_I 0x00
50 #define INDEX_WRITEBACK_INV_D 0x01
51 #define INDEX_LOAD_TAG_I 0x04
52 #define INDEX_LOAD_TAG_D 0x05
53 #define INDEX_STORE_TAG_I 0x08
54 #define INDEX_STORE_TAG_D 0x09
55 #if defined(CONFIG_CPU_LOONGSON2)
56 #define HIT_INVALIDATE_I 0x00
57 #else
58 #define HIT_INVALIDATE_I 0x10
59 #endif
60 #define HIT_INVALIDATE_D 0x11
61 #define HIT_WRITEBACK_INV_D 0x15
62
63 /*
64 * R4000-specific cacheops
65 */
66 #define CREATE_DIRTY_EXCL_D 0x0d
67 #define FILL 0x14
68 #define HIT_WRITEBACK_I 0x18
69 #define HIT_WRITEBACK_D 0x19
70
71 /*
72 * R4000SC and R4400SC-specific cacheops
73 */
74 #define INDEX_INVALIDATE_SI 0x02
75 #define INDEX_WRITEBACK_INV_SD 0x03
76 #define INDEX_LOAD_TAG_SI 0x06
77 #define INDEX_LOAD_TAG_SD 0x07
78 #define INDEX_STORE_TAG_SI 0x0A
79 #define INDEX_STORE_TAG_SD 0x0B
80 #define CREATE_DIRTY_EXCL_SD 0x0f
81 #define HIT_INVALIDATE_SI 0x12
82 #define HIT_INVALIDATE_SD 0x13
83 #define HIT_WRITEBACK_INV_SD 0x17
84 #define HIT_WRITEBACK_SD 0x1b
85 #define HIT_SET_VIRTUAL_SI 0x1e
86 #define HIT_SET_VIRTUAL_SD 0x1f
87
88 /*
89 * R5000-specific cacheops
90 */
91 #define R5K_PAGE_INVALIDATE_S 0x17
92
93 /*
94 * RM7000-specific cacheops
95 */
96 #define PAGE_INVALIDATE_T 0x16
97
98 /*
99 * R10000-specific cacheops
100 *
101 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
102 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
103 */
104 #define INDEX_WRITEBACK_INV_S 0x03
105 #define INDEX_LOAD_TAG_S 0x07
106 #define INDEX_STORE_TAG_S 0x0B
107 #define HIT_INVALIDATE_S 0x13
108 #define CACHE_BARRIER 0x14
109 #define HIT_WRITEBACK_INV_S 0x17
110 #define INDEX_LOAD_DATA_I 0x18
111 #define INDEX_LOAD_DATA_D 0x19
112 #define INDEX_LOAD_DATA_S 0x1b
113 #define INDEX_STORE_DATA_I 0x1c
114 #define INDEX_STORE_DATA_D 0x1d
115 #define INDEX_STORE_DATA_S 0x1f
116
117 #endif /* __ASM_CACHEOPS_H */
118