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Searched refs:CSITE_CPU_DBG1_LAR (Results 1 – 4 of 4) sorted by relevance

/arch/arm/include/asm/arch-tegra/
A Dap.h32 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) macro
/arch/arm/mach-tegra/
A Dcpu.h41 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) macro
A Dcpu.c441 writel(rst, CSITE_CPU_DBG1_LAR); in clock_enable_coresight()
/arch/arm/mach-tegra/tegra20/
A Dwarmboot_avp.c135 writel(reg, CSITE_CPU_DBG1_LAR); in wb_start()

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