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/arch/arm/dts/
A Dstm32h750i-art-pi-u-boot.dtsi34 pinmux = <STM32_PINMUX('D', 0, AF12)>,
35 <STM32_PINMUX('D', 1, AF12)>,
36 <STM32_PINMUX('D', 8, AF12)>,
37 <STM32_PINMUX('D', 9, AF12)>,
38 <STM32_PINMUX('D',10, AF12)>,
39 <STM32_PINMUX('D',14, AF12)>,
40 <STM32_PINMUX('D',15, AF12)>,
A Dstm32h743i-disco-u-boot.dtsi35 pinmux = <STM32_PINMUX('D', 0, AF12)>,
36 <STM32_PINMUX('D', 1, AF12)>,
37 <STM32_PINMUX('D', 8, AF12)>,
38 <STM32_PINMUX('D', 9, AF12)>,
39 <STM32_PINMUX('D',10, AF12)>,
40 <STM32_PINMUX('D',14, AF12)>,
41 <STM32_PINMUX('D',15, AF12)>,
A Dstm32h743i-eval-u-boot.dtsi35 pinmux = <STM32_PINMUX('D', 0, AF12)>,
36 <STM32_PINMUX('D', 1, AF12)>,
37 <STM32_PINMUX('D', 8, AF12)>,
38 <STM32_PINMUX('D', 9, AF12)>,
39 <STM32_PINMUX('D',10, AF12)>,
40 <STM32_PINMUX('D',14, AF12)>,
41 <STM32_PINMUX('D',15, AF12)>,
A Dstm32f746-disco-u-boot.dtsi97 pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
98 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
99 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
109 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
110 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
111 <STM32_PINMUX('D',15, AF12)>, /* D1 */
112 <STM32_PINMUX('D',14, AF12)>, /* D0 */
147 <STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
148 <STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
149 <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
A Dstm32h747i-disco-u-boot.dtsi38 pinmux = <STM32_PINMUX('D', 0, AF12)>,
39 <STM32_PINMUX('D', 1, AF12)>,
40 <STM32_PINMUX('D', 8, AF12)>,
41 <STM32_PINMUX('D', 9, AF12)>,
42 <STM32_PINMUX('D',10, AF12)>,
43 <STM32_PINMUX('D',14, AF12)>,
44 <STM32_PINMUX('D',15, AF12)>,
A Dstm32f429-disco-u-boot.dtsi138 pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
139 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
140 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
150 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
151 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
152 <STM32_PINMUX('D',15, AF12)>, /* D01 */
153 <STM32_PINMUX('D',14, AF12)>, /* D00 */
A Dstm32f769-disco-u-boot.dtsi101 <STM32_PINMUX('D',10, AF12)>, /* D15 */
102 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
103 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
113 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
114 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
115 <STM32_PINMUX('D',15, AF12)>, /* D1 */
116 <STM32_PINMUX('D',14, AF12)>, /* D0 */
155 <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
A Dstm32429i-eval-u-boot.dtsi170 <STM32_PINMUX('D',10, AF12)>, /* D15 */
171 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
172 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
182 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
183 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
184 <STM32_PINMUX('D',15, AF12)>, /* D01 */
185 <STM32_PINMUX('D',14, AF12)>, /* D00 */
A Dstm32746g-eval-u-boot.dtsi98 <STM32_PINMUX('D',10, AF12)>, /* D15 */
99 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
100 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
110 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
111 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
112 <STM32_PINMUX('D',15, AF12)>, /* D1 */
113 <STM32_PINMUX('D',14, AF12)>, /* D0 */
A Dstm32f469-disco-u-boot.dtsi174 <STM32_PINMUX('D',10, AF12)>, /* D15 */
175 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
176 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
186 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
187 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
188 <STM32_PINMUX('D',15, AF12)>, /* D01 */
189 <STM32_PINMUX('D',14, AF12)>, /* D00 */
A Duniphier-ld6b.dtsi9 * LD6b consists of two silicon dies: D-chip and A-chip.
10 * The D-chip (digital chip) is the same as the PXs2 die.
A Domap3-igep0020-u-boot.dtsi5 * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
A Domap3-devkit8000-u-boot.dtsi5 * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
A Domap3-evm-37xx-u-boot.dtsi5 * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
A Domap3-evm-u-boot.dtsi5 * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
/arch/x86/include/asm/arch-baytrail/acpi/
A Dirqroute.h17 PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
20 PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
22 PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
23 PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
26 PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D)
A Dusb.asl18 /* Highest D state in S3 state */
21 /* Highest D state in S4 state */
A Dxhci.asl18 /* Highest D state in S3 state */
/arch/x86/include/asm/arch-quark/acpi/
A Dirqroute.h11 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
14 PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
/arch/powerpc/cpu/mpc83xx/bats/
A DKconfig75 bool "D-cache Write-through"
78 bool "D-cache Inhibited"
84 bool "D-cache Guarded"
223 bool "D-cache Inhibited"
229 bool "D-cache Guarded"
374 bool "D-cache Guarded"
519 bool "D-cache Guarded"
666 bool "D-cache Guarded"
811 bool "D-cache Guarded"
956 bool "D-cache Guarded"
[all …]
/arch/mips/mach-octeon/include/mach/
A Dcvmx-global-resources.h66 #define TAG_INIT_PART(A, B, C, D, E, F, G, H) \ argument
68 (((u64)(D) & 0xff) << 32) | (((u64)(E) & 0xff) << 24) | (((u64)(F) & 0xff) << 16) | \
/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.pci_iommu_extra14 - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number
16 - for hot-plug case, specify the B.D.F with which the device will show up on
29 <bdf> identifies to which B.D.F the action applies to
/arch/arm/mach-meson/
A DKconfig37 Select this if your SoC is an S905X/D or S805X
51 Select this if your SoC is an A113X/D
/arch/arc/
A DKconfig33 bool "ARC 750D"
40 bool "ARC 770D"
87 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
/arch/mips/dts/
A Dnexys4ddr.dts27 local-mac-address = [08 86 4C 0D F7 09];

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