Searched refs:DDR3PHY_CTRL_PHY_RESET_OFF (Results 1 – 2 of 2) sorted by relevance
| /arch/arm/mach-exynos/ | ||
| A D | exynos5_setup.h | 252 #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) macro |
| A D | dmc_init_ddr3.c | 30 writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); in reset_phy_ctrl() |
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