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Searched refs:DDR_MODE_DDR3 (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-exynos/
A Ddmc_common.c79 if (mode == DDR_MODE_DDR3) { in update_reset_dll()
163 if (param->mem_type == DDR_MODE_DDR3) { in mem_ctrl_init()
A Ddmc_init_ddr3.c76 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
101 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
210 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
492 val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
497 val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
566 update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
567 update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
A Dclock_init_exynos5.c139 .mem_type = DDR_MODE_DDR3,
265 .mem_type = DDR_MODE_DDR3,
368 .mem_type = DDR_MODE_DDR3,
/arch/arm/mach-exynos/include/mach/
A Ddmc.h433 DDR_MODE_DDR3, enumerator

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