Home
last modified time | relevance | path

Searched refs:DDR_PLL_CONFIG_PLLPWD_MASK (Results 1 – 1 of 1) sorted by relevance

/arch/mips/mach-ath79/qca956x/
A Dclk.c77 #define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000 macro
79 (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
263 ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(1)); in qca956x_pll_init()
288 ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(0)); in qca956x_pll_init()

Completed in 4 milliseconds