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Searched refs:DRAM_APB_CLK_ROOT (Results 1 – 8 of 8) sorted by relevance

/arch/arm/include/asm/arch-imx8m/
A Dclock_imx8mm.h92 DRAM_APB_CLK_ROOT = 65, enumerator
182 DRAM_APB_CLK_ROOT = 65, enumerator
263 DRAM_APB_CLK_ROOT = 65, enumerator
A Dclock_imx8mq.h53 DRAM_APB_CLK_ROOT = 65, enumerator
/arch/arm/include/asm/arch-imx9/
A Dccm_regs.h88 #define DRAM_APB_CLK_ROOT 77 macro
/arch/arm/mach-imx/imx8m/
A Dclock_imx8mm.c167 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_enable_bypass()
178 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_disable_bypass()
493 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in clock_init()
A Dclock_imx8mq.c598 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_enable_bypass()
609 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_disable_bypass()
A Dclock_slice.c125 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
584 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
1018 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
1382 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
/arch/arm/mach-imx/imx9/
A Dclock.c677 ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); in dram_enable_bypass()
685 ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); in dram_disable_bypass()
A Dclock_root.c111 { DRAM_APB_CLK_ROOT, 1 },

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