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/arch/arm/dts/
A Darmada-8040-mcbin.dts92 * [49] 10G port 1 interrupt
94 * [51] 2.5G SFP TX fault
96 * [53] 2.5G SFP mode
97 * [54] 2.5G SFP LOS
171 * Lane 4: SFI (10G)
222 * [8] CP1 10G SFP LOS
223 * [9] CP1 10G PHY RESET
225 * [11] CP1 10G SFP Mode
233 * [27] CP0 10G SFP Mode
234 * [28] CP0 10G SFP LOS
[all …]
A Dstm32h750i-art-pi-u-boot.dtsi66 <STM32_PINMUX('G', 0, AF12)>,
67 <STM32_PINMUX('G', 1, AF12)>,
68 <STM32_PINMUX('G', 2, AF12)>,
69 <STM32_PINMUX('G', 4, AF12)>,
70 <STM32_PINMUX('G', 5, AF12)>,
71 <STM32_PINMUX('G', 8, AF12)>,
72 <STM32_PINMUX('G',15, AF12)>,
A Dstm32h743i-disco-u-boot.dtsi67 <STM32_PINMUX('G', 0, AF12)>,
68 <STM32_PINMUX('G', 1, AF12)>,
69 <STM32_PINMUX('G', 2, AF12)>,
70 <STM32_PINMUX('G', 4, AF12)>,
71 <STM32_PINMUX('G', 5, AF12)>,
72 <STM32_PINMUX('G', 8, AF12)>,
73 <STM32_PINMUX('G',15, AF12)>,
A Dstm32h743i-eval-u-boot.dtsi67 <STM32_PINMUX('G', 0, AF12)>,
68 <STM32_PINMUX('G', 1, AF12)>,
69 <STM32_PINMUX('G', 2, AF12)>,
70 <STM32_PINMUX('G', 4, AF12)>,
71 <STM32_PINMUX('G', 5, AF12)>,
72 <STM32_PINMUX('G', 8, AF12)>,
73 <STM32_PINMUX('G',15, AF12)>,
A Dstm32h747i-disco-u-boot.dtsi70 <STM32_PINMUX('G', 0, AF12)>,
71 <STM32_PINMUX('G', 1, AF12)>,
72 <STM32_PINMUX('G', 2, AF12)>,
73 <STM32_PINMUX('G', 4, AF12)>,
74 <STM32_PINMUX('G', 5, AF12)>,
75 <STM32_PINMUX('G', 8, AF12)>,
76 <STM32_PINMUX('G',15, AF12)>,
A Dstm32f746-disco-u-boot.dtsi82 pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
83 <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
84 <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
117 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
118 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
120 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
121 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
136 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
138 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dstm32746g-eval-u-boot.dtsi63 <STM32_PINMUX('G',13, AF11)>, /*ETH_MII_TXD0 */
64 <STM32_PINMUX('G',14, AF11)>, /*ETH_MII_TXD1 */
72 <STM32_PINMUX('G',11, AF11)>, /*ETH_MII_TX_EN */
120 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
121 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
123 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
124 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
139 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
141 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dstm32f769-disco-u-boot.dtsi69 pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
70 <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
71 <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
123 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
124 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
126 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
127 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
142 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
144 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dstm32429i-eval-u-boot.dtsi192 <STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */
193 <STM32_PINMUX('G', 4, AF12)>, /* A14-BA0 */
194 <STM32_PINMUX('G', 3, AF12)>, /* A13 */
195 <STM32_PINMUX('G', 2, AF12)>, /* A12 */
196 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
197 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
212 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
214 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dstm32f429-disco-u-boot.dtsi158 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
159 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
161 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
162 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
177 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
179 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
A Darmada-xp-crs305-1g-4s.dts3 * Device Tree file for MikroTik CRS305-1G-4S+ board
12 model = "MikroTik CRS305-1G-4S+";
A Darmada-xp-crs326-24g-2s.dts3 * Device Tree file for MikroTik CRS326-24G-2S+ board
12 model = "MikroTik CRS326-24G-2S+";
A Darmada-8040-puzzle-m801.dts99 * [42,43] XSMI (controls two 10G phys)
102 * [49] 10G port 1 interrupt
103 * [50] 10G port 0 interrupt
104 * [51] 2.5G SFP TX fault
106 * [53] 2.5G SFP mode
107 * [54] 2.5G SFP LOS
219 * Lane 4: SFI (10G)
360 * Lane 4: SFI (10G)
A Darmada-xp-crs305-1g-4s-bit.dts3 * Device Tree file for MikroTik CRS305-1G-4S+ Bit board
12 model = "MikroTik CRS305-1G-4S+ Bit";
A Darmada-xp-crs326-24g-2s-bit.dts3 * Device Tree file for MikroTik CRS326-24G-2S+ Bit board
12 model = "MikroTik CRS326-24G-2S+ Bit";
A Dstm32f469-disco-u-boot.dtsi196 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
197 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
199 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
200 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
215 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
217 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
A Dtegra20-motorola-olympus.dts7 model = "Motorola Atrix 4G (MB860)";
A Darmada-8040-clearfog-gt-8k.dts157 * Lane 2: SFI0 (10G)
187 /* 10G SFI SFP */
222 * [29] CP0 10G SFP TX Disable
310 /* 1G SGMII */
318 /* 2.5G to Topaz switch */
A Darmada-xp-crs305-1g-4s.dtsi3 * Device Tree file for CRS305-1G-4S board
24 model = "CRS305-1G-4S+";
A Darmada-xp-crs326-24g-2s.dtsi3 * Device Tree file for CRS326-24G-2S board
24 model = "CRS326-24G-2S+";
A Dimx6qdl-dhcom-pdk2.dtsi27 enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
184 /* 1G ethernet */
285 * G: backlight enable
308 pinctrl_enet_1G: enet-1G-grp {
/arch/x86/include/asm/arch-quark/acpi/
A Dirqroute.h9 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
10 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
/arch/arm/mach-rockchip/rk3588/
A DKconfig19 - 1x RTL8125B 2.5G Ethernet
79 There are tree variants depending on the DRAM size : 8G and 16G.
99 There are four variants depending on the DRAM size: 4G/32GB eMMC,
100 8G/64GB eMMC, 16G/16MB SPI NOR, and 16G/256GB eMMC/16MB SPI NOR
114 Ethernet: PCIe 2.5G 2x Ethernet (RTL8125BG)
117 4G Module: MiniPCIe x1, MicroSIM Card Slot x1
200 There are tree variants depending on the DRAM size : 4G, 8G and 16G.
226 There are tree variants depending on the DRAM size : 4G, 8G and 16G.
250 There are variants depending on the DRAM size : from 4G up to 32G.
296 There are two variants depending on the DRAM size : 8G and 16G.
[all …]
/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.soc34 - Up to 1 x 10GBase-R supporting 10G interface
191 - Support for 10G operation
262 c) 5 * 1/10G + 5 *1G WRIOP
296 Support for 10G-SXGMII (aka USXGMII).
299 Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
300 Support for XLAUI (and 40GBase-KR4) for 40G.
356 - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one
357 ethernet MAC supporting 1G, 100M, 10M.
361 - Support for 10G-SXGMII and 10G-QXGMII.
401 Support for 10G-SXGMII (aka USXGMII).
[all …]
/arch/mips/mach-octeon/include/mach/
A Dcvmx-global-resources.h66 #define TAG_INIT_PART(A, B, C, D, E, F, G, H) \ argument
69 (((u64)(G) & 0xff) << 8) | (((u64)(H) & 0xff)))

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