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/arch/arm/dts/
A Dstm32h743i-disco-u-boot.dtsi75 <STM32_PINMUX('H', 5, AF12)>,
76 <STM32_PINMUX('H', 6, AF12)>,
77 <STM32_PINMUX('H', 7, AF12)>,
78 <STM32_PINMUX('H', 8, AF12)>,
79 <STM32_PINMUX('H', 9, AF12)>,
80 <STM32_PINMUX('H',10, AF12)>,
81 <STM32_PINMUX('H',11, AF12)>,
82 <STM32_PINMUX('H',12, AF12)>,
83 <STM32_PINMUX('H',13, AF12)>,
84 <STM32_PINMUX('H',14, AF12)>,
[all …]
A Dstm32h743i-eval-u-boot.dtsi75 <STM32_PINMUX('H', 5, AF12)>,
76 <STM32_PINMUX('H', 6, AF12)>,
77 <STM32_PINMUX('H', 7, AF12)>,
78 <STM32_PINMUX('H', 8, AF12)>,
79 <STM32_PINMUX('H', 9, AF12)>,
80 <STM32_PINMUX('H',10, AF12)>,
81 <STM32_PINMUX('H',11, AF12)>,
82 <STM32_PINMUX('H',12, AF12)>,
83 <STM32_PINMUX('H',13, AF12)>,
84 <STM32_PINMUX('H',14, AF12)>,
[all …]
A Dstm32h747i-disco-u-boot.dtsi78 <STM32_PINMUX('H', 5, AF12)>,
79 <STM32_PINMUX('H', 6, AF12)>,
80 <STM32_PINMUX('H', 7, AF12)>,
81 <STM32_PINMUX('H', 8, AF12)>,
82 <STM32_PINMUX('H', 9, AF12)>,
83 <STM32_PINMUX('H',10, AF12)>,
84 <STM32_PINMUX('H',11, AF12)>,
85 <STM32_PINMUX('H',12, AF12)>,
86 <STM32_PINMUX('H',13, AF12)>,
87 <STM32_PINMUX('H',14, AF12)>,
[all …]
A Dstm32746g-eval-u-boot.dtsi70 <STM32_PINMUX('H', 6, AF11)>, /*ETH_MII_RXD2 */
89 <STM32_PINMUX('H',15, AF12)>, /* D23 */
90 <STM32_PINMUX('H',14, AF12)>, /* D22 */
91 <STM32_PINMUX('H',13, AF12)>, /* D21 */
92 <STM32_PINMUX('H',12, AF12)>, /* D20 */
93 <STM32_PINMUX('H',11, AF12)>, /* D19 */
94 <STM32_PINMUX('H',10, AF12)>, /* D18 */
95 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
96 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
136 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
[all …]
A Dstm32429i-eval-u-boot.dtsi161 <STM32_PINMUX('H',15, AF12)>, /* D23 */
162 <STM32_PINMUX('H',14, AF12)>, /* D22 */
163 <STM32_PINMUX('H',13, AF12)>, /* D21 */
164 <STM32_PINMUX('H',12, AF12)>, /* D20 */
165 <STM32_PINMUX('H',11, AF12)>, /* D19 */
166 <STM32_PINMUX('H',10, AF12)>, /* D18 */
167 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
168 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
209 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
210 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
[all …]
A Dstm32f769-disco-u-boot.dtsi92 <STM32_PINMUX('H',15, AF12)>, /* D23 */
93 <STM32_PINMUX('H',14, AF12)>, /* D22 */
94 <STM32_PINMUX('H',13, AF12)>, /* D21 */
95 <STM32_PINMUX('H',12, AF12)>, /* D20 */
96 <STM32_PINMUX('H',11, AF12)>, /* D19 */
97 <STM32_PINMUX('H',10, AF12)>, /* D18 */
98 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
99 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
139 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
140 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
[all …]
A Dstm32f469-disco-u-boot.dtsi165 <STM32_PINMUX('H',15, AF12)>, /* D23 */
166 <STM32_PINMUX('H',14, AF12)>, /* D22 */
167 <STM32_PINMUX('H',13, AF12)>, /* D21 */
168 <STM32_PINMUX('H',12, AF12)>, /* D20 */
169 <STM32_PINMUX('H',11, AF12)>, /* D19 */
170 <STM32_PINMUX('H',10, AF12)>, /* D18 */
171 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
172 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
212 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
216 <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
A Dstm32f746-disco-u-boot.dtsi133 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
134 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
A Dimx6qdl-dhcom-picoitx.dtsi37 "", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H",
A Dsynquacer-sc2a11-developerbox.dts42 "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J",
A Dstm32h750i-art-pi-u-boot.dtsi74 <STM32_PINMUX('H', 5, AF12)>,
A Dimx6qdl-dhcom-pdk2.dtsi129 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
286 * H: led7
A Dimx8mp-dhcom-picoitx.dts70 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
A Dstm32mp13xx-dhcor-u-boot.dtsi94 <STM32_PINMUX('H', 14, AF4)>; /* I2C3_SDA */
A Dhi3798cv200-poplar.dts124 gpio-line-names = "GPIO-H", "GPIO-I",
A Dtegra124-nyan.dtsi58 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
450 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
674 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
A Dtegra20-tamonten.dtsi480 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
481 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
A Dimx6qdl-dhcom-drc02.dtsi48 "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
A Dtegra20-harmony.dts651 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
658 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
659 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
/arch/x86/include/asm/arch-quark/acpi/
A Dirqroute.h9 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
10 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
/arch/mips/mach-octeon/include/mach/
A Dcvmx-global-resources.h66 #define TAG_INIT_PART(A, B, C, D, E, F, G, H) \ argument
69 (((u64)(G) & 0xff) << 8) | (((u64)(H) & 0xff)))
/arch/arm/mach-k3/keys/
A DcustMpk.key35 BbvOpE+bi5EdvEiaFBTtmiBnpjg+pJq+oRU60h/H+c9CNR0lGxY6Fk9An4f+g6xE
A DcustMpk.pem35 BbvOpE+bi5EdvEiaFBTtmiBnpjg+pJq+oRU60h/H+c9CNR0lGxY6Fk9An4f+g6xE
/arch/arm/mach-sunxi/
A DKconfig817 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
820 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
825 uses a bit faster timings than DDR3-1333H).
907 bool "Pins for mmc1 are on Port H"
910 Select this option for boards where mmc1 uses the Port H pinmux.
1018 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
1050 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
1058 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
1067 port H.
1075 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
/arch/arm/mach-rockchip/rk3588/
A DKconfig107 VPU: 8K@60fps H.265 and VP9 decoder, 8K@30fps H.264 decoder,
108 4K@60fps AV1 decoder, 8K@30fps H.264 and H.265 encoder

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