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Searched refs:KS2_PSC_BASE (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-keystone/
A Dpsc.c53 ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT); in psc_wait()
106 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_state()
130 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
133 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
136 ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); in psc_set_state()
138 __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); in psc_set_state()
208 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_reset_iso()
229 ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); in psc_disable_domain()
231 __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD); in psc_disable_domain()
271 ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); in psc_module_keep_in_reset_enabled()
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A Dddr3.c414 tmp_a = __raw_readl(KS2_PSC_BASE + in ddr3_err_reset_workaround()
418 __raw_writel(tmp_a, KS2_PSC_BASE + in ddr3_err_reset_workaround()
425 tmp_b = __raw_readl(KS2_PSC_BASE + in ddr3_err_reset_workaround()
428 __raw_writel(tmp_b, KS2_PSC_BASE + in ddr3_err_reset_workaround()
/arch/arm/mach-keystone/include/mach/
A Dhardware.h163 #define KS2_PSC_BASE 0x02350000 macro

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