Home
last modified time | relevance | path

Searched refs:LDELAY (Results 1 – 8 of 8) sorted by relevance

/arch/arm/mach-omap2/omap3/
A Dclock.c138 LDELAY); in dpll3_init_34xx()
192 LDELAY); in dpll3_init_34xx()
294 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_34xx()
305 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_34xx()
395 LDELAY); in dpll3_init_36xx()
442 LDELAY); in dpll3_init_36xx()
534 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_36xx()
648 LDELAY); in prcm_init()
660 LDELAY); in prcm_init()
678 LDELAY); in prcm_init()
[all …]
/arch/arm/mach-omap2/am33xx/
A Dclock.c45 (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { in wait_for_lock()
62 (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { in wait_for_bypass()
123 u32 bound = LDELAY; in wait_for_clk_enable()
151 u32 bound = LDELAY; in wait_for_clk_disable()
/arch/arm/mach-omap2/omap5/
A Ddra7xx_iodelay.c33 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) in isolate_io()
47 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) in isolate_io()
67 (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) in calibrate_iodelay()
79 (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) in update_delay_mechanism()
/arch/arm/include/asm/arch-omap3/
A Dclock.h10 #define LDELAY 12000000 macro
/arch/arm/mach-omap2/
A Dabb.c115 if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY)) in abb_setup()
A Dclocks-common.c117 LDELAY)) { in wait_for_bypass()
136 &dpll_regs->cm_idlest_dpll, LDELAY)) { in wait_for_lock()
681 u32 bound = LDELAY; in wait_for_clk_enable()
710 u32 bound = LDELAY; in wait_for_clk_disable()
760 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) { in freq_update_core()
/arch/arm/include/asm/arch-am33xx/
A Dclock.h16 #define LDELAY 1000000 macro
/arch/arm/include/asm/arch-omap5/
A Dclock.h17 #define LDELAY 1000000 macro

Completed in 14 milliseconds