| /arch/x86/lib/ |
| A D | bios_interrupts.c | 44 M.x86.R_EAX &= 0x00ff; in int10_handler()
45 M.x86.R_ECX = 0x0607; in int10_handler()
64 M.x86.R_EBX &= 0x00ff; in int10_handler()
76 M.x86.R_EAX = 64 * 1024; in int12_handler()
129 M.x86.R_ECX = 0xff; in int1a_handler()
134 devid = M.x86.R_ECX; in int1a_handler()
168 reg = M.x86.R_EDI; in int1a_handler()
180 M.x86.R_ECX = byte; in int1a_handler()
184 M.x86.R_ECX = word; in int1a_handler()
191 byte = M.x86.R_ECX; in int1a_handler()
[all …]
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| A D | bios.c | 68 .eax = M.x86.R_EAX, in int_exception_handler()
69 .ecx = M.x86.R_ECX, in int_exception_handler()
70 .edx = M.x86.R_EDX, in int_exception_handler()
71 .ebx = M.x86.R_EBX, in int_exception_handler()
72 .esp = M.x86.R_ESP, in int_exception_handler()
73 .ebp = M.x86.R_EBP, in int_exception_handler()
74 .esi = M.x86.R_ESI, in int_exception_handler()
79 .cs = M.x86.R_CS, in int_exception_handler()
93 M.x86.intno, M.x86.R_EAX); in int_unknown_handler()
331 M.x86.R_EIP = ip; in interrupt_handler()
[all …]
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| /arch/arm/mach-rockchip/rk3528/ |
| A D | MAINTAINERS | 2 M: Jonas Karlman <jonas@kwiboo.se>
8 M: Jonas Karlman <jonas@kwiboo.se>
|
| /arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| A D | README.lsch3 | 69 | .. Unused .. (7M) | |
77 | AIOP FW (4M) | |
79 | MC DPC Blob (1M) | |
81 | MC DPL Blob (1M) | |
83 | MC FW (4M) | |
87 | BootLoader (1M) | |
89 | RCW and PBI (1M) | |
99 | AIOP FW (4M) | |
101 | MC DPC Blob (1M) | |
103 | MC DPL Blob (1M) | |
[all …]
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| /arch/arm/mach-aspeed/ast2500/ |
| A D | Kconfig | 10 It has 512M of RAM, 32M of SPI flash, two Ethernet ports,
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| /arch/arm/mach-aspeed/ast2600/ |
| A D | Kconfig | 11 It has 512M of RAM, 32M of SPI flash, two Ethernet ports,
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| /arch/arm/mach-rockchip/rv1108/ |
| A D | Kconfig | 16 * 128M DDR3
17 * 64M SPI Nor Flash
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| /arch/arm/mach-rockchip/rk3588/ |
| A D | Kconfig | 20 - 4x M.2 M-Key with PCIe 3.0 x1 (via bifurcation) for NVMe SSDs
43 - PCIE M.2 E Key for RTL8852BE Wireless connection
44 - PCIE M.2 M Key for NVME connection
59 * PCIe M.2 2230 Key M (Gen 2 1-lane) for WiFi+BT
60 * PCIe M.2 2280 Key M (Gen 3 4-lane) for NVMe
113 PCIe 3.0: M.2 M-Key x1, PCIe 3.0 x4 for NVMe SSDs up to 2,500 MB/s
115 PCIe 2.1: M.2 E-Key x1, PCIe 2.1 x1 and USB2.0 Host,
116 supports M.2 WiFi and Bluetooth
144 eMMC storage, one M.2 M-Key connector, one RTL8211F 1GbE and one
261 M.2 M-key and M.2 E-key connector
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| /arch/arc/dts/ |
| A D | skeleton.dtsi | 28 reg = <0x80000000 0x10000000>; /* 256M */
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| /arch/arm/dts/ |
| A D | imx6qdl-dhcom-drc02.dtsi | 74 * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts.
77 cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
121 * M: uart1 cts
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| A D | imx8mq-cm.dts | 78 opp-25M {
82 opp-100M {
87 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
89 opp-166M {
93 opp-800M {
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| A D | uniphier-pro5-4kbox.dts | 3 * Device Tree Source for UniPhier Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
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| A D | imx8mp-dhcom-drc02.dts | 160 * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.
163 cts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */
219 * GPIO M is connected to UART1_CTS
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| A D | fsl-sch-30841.dtsi | 12 * It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
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| A D | tegra186-p2771-0000.dtsi | 31 phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
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| A D | k3-am65-iot2050-boot-image.dtsi | 239 description = "M.2-bkey-usb3-overlay";
253 description = "M.2-bkey-ekey-pcie-overlay";
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| A D | imx8mm-kontron-sl.dtsi | 49 opp-100M {
53 opp-750M {
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| A D | usb_a9263.dts | 16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
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| A D | imx8mm-kontron-osm-s.dtsi | 55 opp-100M {
59 opp-750M {
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| A D | at91sam9g45-gurnard.dts | 16 bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
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| A D | at91sam9263ek.dts | 16 bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
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| /arch/arm/mach-sunxi/ |
| A D | clock_sun4i.c | 79 #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ argument
90 (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
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| /arch/riscv/dts/ |
| A D | thead-th1520-binman.dtsi | 27 description = "Configuration to load M-mode U-Boot";
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| /arch/arm/mach-omap2/ |
| A D | clocks-common.c | 215 u32 temp, M, N; in do_setup_dpll() local
229 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT; in do_setup_dpll()
231 if ((M != (params->m)) || (N != (params->n))) { in do_setup_dpll()
235 M, N); in do_setup_dpll()
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| /arch/x86/cpu/apollolake/ |
| A D | Kconfig | 105 use the SPI-flash driver to load SPL, U-Boot and FSP-M. For technical
|