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Searched refs:MCHBAR_REG (Results 1 – 12 of 12) sorted by relevance

/arch/x86/cpu/ivybridge/
A Dnorthbridge.c116 bridge_type = readl(MCHBAR_REG(0x5f10)); in northbridge_init()
121 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); in northbridge_init()
129 writel(bridge_type, MCHBAR_REG(0x5f10)); in northbridge_init()
135 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); in northbridge_init()
149 writel(msr.lo, MCHBAR_REG(0x59A0)); in northbridge_init()
150 writel(msr.hi, MCHBAR_REG(0x59A4)); in northbridge_init()
154 writel(0x00100001, MCHBAR_REG(0x5500)); in northbridge_init()
198 writel(IOMMU_BASE1 >> 32, MCHBAR_REG(0x5404)); in sandybridge_init_iommu()
199 writel(IOMMU_BASE1 | 1, MCHBAR_REG(0x5400)); in sandybridge_init_iommu()
200 writel(IOMMU_BASE2 >> 32, MCHBAR_REG(0x5414)); in sandybridge_init_iommu()
[all …]
A Dcpu.c136 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { in checkcpu()
A Dsdram.c202 setbits_le32(MCHBAR_REG(0x7010), 1); in post_system_agent_init()
557 writew(0xCAFE, MCHBAR_REG(SSKPD)); in dram_init()
/arch/x86/cpu/apollolake/
A Dpunit.c39 writel(0, MCHBAR_REG(CORE_DISABLE_MASK)); in punit_init()
42 reg = readl(MCHBAR_REG(BIOS_RESET_CPL)); in punit_init()
55 MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ)); in punit_init()
66 while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) { in punit_init()
A Dacpi.c155 u64 gfxvtbar = readq(MCHBAR_REG(GFXVTBAR)) & VTBAR_MASK; in apl_acpi_fill_dmar()
156 u64 defvtbar = readq(MCHBAR_REG(DEFVTBAR)) & VTBAR_MASK; in apl_acpi_fill_dmar()
157 bool gfxvten = readl(MCHBAR_REG(GFXVTBAR)) & VTBAR_ENABLED; in apl_acpi_fill_dmar()
158 bool defvten = readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED; in apl_acpi_fill_dmar()
A Dsystemagent.c21 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); in enable_bios_reset_cpl()
A Dfsp_s.c128 writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL)); in set_power_limits()
129 writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4)); in set_power_limits()
A Dhostbridge.c289 !(readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED)) in apl_acpi_hb_write_tables()
/arch/x86/cpu/broadwell/
A Dcpu_full.c106 if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & in pcode_ready()
136 return readl(MCHBAR_REG(BIOS_MAILBOX_DATA)); in pcode_mailbox_read()
149 writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA)); in pcode_mailbox_write()
246 writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA)); in calibrate_24mhz_bclk()
248 MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); in calibrate_24mhz_bclk()
260 MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); in calibrate_24mhz_bclk()
267 readl(MCHBAR_REG(BIOS_MAILBOX_DATA))); in calibrate_24mhz_bclk()
612 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO)); in cpu_set_power_limits()
613 writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI)); in cpu_set_power_limits()
616 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO)); in cpu_set_power_limits()
[all …]
A Dpch.c448 clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ in systemagent_init()
454 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); in systemagent_init()
/arch/x86/cpu/intel_common/
A Dmrc.c107 addr_decoder_common = readl(MCHBAR_REG(0x5000)); in report_memory_config()
108 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); in report_memory_config()
109 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); in report_memory_config()
112 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); in report_memory_config()
244 version = readl(MCHBAR_REG(MCHBAR_PEI_VERSION)); in sdram_initialise()
/arch/x86/include/asm/
A Dintel_regs.h12 #define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg)) macro

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