Searched refs:MCH_BASE_ADDRESS (Results 1 – 9 of 9) sorted by relevance
| /arch/x86/include/asm/ |
| A D | intel_regs.h | 10 #define MCH_BASE_ADDRESS 0xfed10000 macro
12 #define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
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| /arch/x86/include/asm/arch-apollolake/acpi/ |
| A D | pmc_ipc.asl | 39 Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA)
41 Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
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| /arch/x86/cpu/broadwell/ |
| A D | northbridge.c | 119 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); in broadwell_northbridge_early_init()
122 writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR); in broadwell_northbridge_early_init()
123 writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR); in broadwell_northbridge_early_init()
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| /arch/x86/include/asm/arch-apollolake/ |
| A D | iomap.h | 24 #define MCH_BASE_ADDRESS 0xfed10000 macro
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| /arch/x86/include/asm/arch-broadwell/ |
| A D | iomap.h | 16 #define MCH_BASE_ADDRESS 0xfed10000 macro
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| /arch/x86/cpu/ivybridge/ |
| A D | northbridge.c | 163 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); in sandybridge_setup_northbridge_bars()
164 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); in sandybridge_setup_northbridge_bars()
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| A D | sdram.c | 409 .mchbar = MCH_BASE_ADDRESS, in dram_init()
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| /arch/x86/cpu/apollolake/ |
| A D | hostbridge.c | 166 base = MCH_BASE_ADDRESS; in apl_hostbridge_early_init()
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| /arch/x86/dts/ |
| A D | chromebook_coral.dts | 104 MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>;
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