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Searched refs:MPLL_CON0_VAL (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init_exynos4.c86 writel(MPLL_CON0_VAL, &clk->mpll_con0); in system_clock_init()
A Dexynos4_setup.h345 #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) macro

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