1 /* SPDX-License-Identifier: Intel */ 2 /* 3 * Copyright (C) 2013, Intel Corporation 4 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 5 * 6 * Ported from Intel released Quark UEFI BIOS 7 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei 8 */ 9 10 #ifndef _MRC_H_ 11 #define _MRC_H_ 12 13 #include <linux/types.h> 14 15 #define MRC_VERSION 0x0111 16 17 /* architectural definitions */ 18 #define NUM_CHANNELS 1 /* number of channels */ 19 #define NUM_RANKS 2 /* number of ranks per channel */ 20 #define NUM_BYTE_LANES 4 /* number of byte lanes per channel */ 21 22 /* software limitations */ 23 #define MAX_CHANNELS 1 24 #define MAX_RANKS 2 25 #define MAX_BYTE_LANES 4 26 27 #define MAX_SOCKETS 1 28 #define MAX_SIDES 1 29 #define MAX_ROWS (MAX_SIDES * MAX_SOCKETS) 30 31 /* Specify DRAM and channel width */ 32 enum { 33 X8, /* DRAM width */ 34 X16, /* DRAM width & Channel Width */ 35 X32 /* Channel Width */ 36 }; 37 38 /* Specify DRAM speed */ 39 enum { 40 DDRFREQ_800, 41 DDRFREQ_1066 42 }; 43 44 /* Specify DRAM type */ 45 enum { 46 DDR3, 47 DDR3L 48 }; 49 50 /* 51 * density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb 52 * cl: DRAM CAS Latency in clocks 53 * ras: ACT to PRE command period 54 * wtr: Delay from start of internal write transaction to internal read command 55 * rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K) 56 * faw: Four activate window (JESD79 specific to page size 1K/2K) 57 * 58 * ras/wtr/rrd/faw timings are in picoseconds 59 * 60 * Refer to JEDEC spec (or DRAM datasheet) when changing these values. 61 */ 62 struct dram_params { 63 uint8_t density; 64 uint8_t cl; 65 uint32_t ras; 66 uint32_t wtr; 67 uint32_t rrd; 68 uint32_t faw; 69 }; 70 71 /* 72 * Delay configuration for individual signals 73 * Vref setting 74 * Scrambler seed 75 */ 76 struct mrc_timings { 77 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; 78 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; 79 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; 80 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; 81 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES]; 82 uint32_t wctl[NUM_CHANNELS][NUM_RANKS]; 83 uint32_t wcmd[NUM_CHANNELS]; 84 uint32_t scrambler_seed; 85 /* need to save for the case of frequency change */ 86 uint8_t ddr_speed; 87 }; 88 89 /* Boot mode defined as bit mask (1<<n) */ 90 enum { 91 BM_UNKNOWN, 92 BM_COLD = 1, /* full training */ 93 BM_FAST = 2, /* restore timing parameters */ 94 BM_S3 = 4, /* resume from S3 */ 95 BM_WARM = 8 96 }; 97 98 /* MRC execution status */ 99 #define MRC_SUCCESS 0 /* initialization ok */ 100 #define MRC_E_MEMTEST 1 /* memtest failed */ 101 102 /* 103 * Memory Reference Code parameters 104 * 105 * It includes 3 parts: 106 * - input parameters like boot mode and DRAM parameters 107 * - context parameters for MRC internal state 108 * - output parameters like initialization result and memory size 109 */ 110 struct mrc_params { 111 /* Input parameters */ 112 uint32_t boot_mode; /* BM_COLD, BM_FAST, BM_WARM, BM_S3 */ 113 /* DRAM parameters */ 114 uint8_t dram_width; /* x8, x16 */ 115 uint8_t ddr_speed; /* DDRFREQ_800, DDRFREQ_1066 */ 116 uint8_t ddr_type; /* DDR3, DDR3L */ 117 uint8_t ecc_enables; /* 0, 1 (memory size reduced to 7/8) */ 118 uint8_t scrambling_enables; /* 0, 1 */ 119 /* 1, 3 (1'st rank has to be populated if 2'nd rank present) */ 120 uint32_t rank_enables; 121 uint32_t channel_enables; /* 1 only */ 122 uint32_t channel_width; /* x16 only */ 123 /* 0, 1, 2 (mode 2 forced if ecc enabled) */ 124 uint32_t address_mode; 125 /* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */ 126 uint8_t refresh_rate; 127 /* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */ 128 uint8_t sr_temp_range; 129 /* 130 * RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED 131 * (select MRS1.DIC driver impedance control) 132 */ 133 uint8_t ron_value; 134 /* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ 135 uint8_t rtt_nom_value; 136 /* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ 137 uint8_t rd_odt_value; 138 struct dram_params params; 139 /* Internally used context parameters */ 140 uint32_t board_id; /* board layout (use x8 or x16 memory) */ 141 uint32_t hte_setup; /* when set hte reconfiguration requested */ 142 uint32_t menu_after_mrc; 143 uint32_t power_down_disable; 144 uint32_t tune_rcvn; 145 uint32_t channel_size[NUM_CHANNELS]; 146 uint32_t column_bits[NUM_CHANNELS]; 147 uint32_t row_bits[NUM_CHANNELS]; 148 uint32_t mrs1; /* register content saved during training */ 149 uint8_t first_run; 150 /* Output parameters */ 151 /* initialization result (non zero specifies error code) */ 152 uint32_t status; 153 /* total memory size in bytes (excludes ECC banks) */ 154 uint32_t mem_size; 155 /* training results (also used on input) */ 156 struct mrc_timings timings; 157 }; 158 159 /* 160 * MRC memory initialization structure 161 * 162 * post_code: a 16-bit post code of a specific initialization routine 163 * boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3 164 * init_fn: real memory initialization routine 165 */ 166 struct mem_init { 167 uint16_t post_code; 168 uint16_t boot_path; 169 void (*init_fn)(struct mrc_params *mrc_params); 170 }; 171 172 /* MRC platform data flags */ 173 #define MRC_FLAG_ECC_EN 0x00000001 174 #define MRC_FLAG_SCRAMBLE_EN 0x00000002 175 #define MRC_FLAG_MEMTEST_EN 0x00000004 176 /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ 177 #define MRC_FLAG_TOP_TREE_EN 0x00000008 178 /* If set ODR signal is asserted to DRAM devices on writes */ 179 #define MRC_FLAG_WR_ODT_EN 0x00000010 180 181 /** 182 * mrc_init - Memory Reference Code initialization entry routine 183 * 184 * @mrc_params: parameters for MRC 185 */ 186 void mrc_init(struct mrc_params *mrc_params); 187 188 #endif /* _MRC_H_ */ 189