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Searched refs:PCIEXBAR (Results 1 – 5 of 5) sorted by relevance

/arch/x86/include/asm/arch-broadwell/
A Dpch.h17 #define PCIEXBAR 0x60 macro
37 #define PCIEXBAR 0x60 macro
/arch/x86/cpu/ivybridge/
A Dnorthbridge.c45 dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg); in get_pcie_bar()
166 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); in sandybridge_setup_northbridge_bars()
167 dm_pci_write_config32(dev, PCIEXBAR + 4, in sandybridge_setup_northbridge_bars()
/arch/x86/cpu/broadwell/
A Dnorthbridge.c115 dm_pci_write_config32(dev, PCIEXBAR + 4, 0); in broadwell_northbridge_early_init()
117 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1); in broadwell_northbridge_early_init()
/arch/x86/cpu/apollolake/
A Dhostbridge.c32 PCIEXBAR = 0x60, enumerator
173 pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32); in apl_hostbridge_early_init()
190 pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32); in apl_hostbridge_early_init()
/arch/x86/include/asm/arch-ivybridge/
A Dsandybridge.h52 #define PCIEXBAR 0x60 macro

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