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Searched refs:PHY_CON0_CTRL_DDR_MODE_MASK (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/include/mach/
A Ddmc.h466 #define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 macro
/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c491 val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
496 val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()

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