PHY_CON0_RESET_VAL (reference) in projects: arch

Searched refs:PHY_CON0_RESET_VAL (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A D	dmc_init_ddr3.c	`138 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init() 148 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init() 169 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init() 690 writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init() 691 writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()`
A D	exynos5_setup.h	`254 #define PHY_CON0_RESET_VAL 0x17020a40 macro`

Completed in 7 milliseconds