Searched refs:PHY_CON1_RESET_VAL (Results 1 – 2 of 2) sorted by relevance
| /arch/arm/mach-exynos/ | ||
| A D | exynos5_setup.h | 259 #define PHY_CON1_RESET_VAL 0x09210100 macro |
| A D | dmc_init_ddr3.c | 176 val = PHY_CON1_RESET_VAL; in ddr3_mem_ctrl_init() |
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