Searched refs:PIRQH (Results 1 – 8 of 8) sorted by relevance
| /arch/x86/dts/ |
| A D | qemu-x86_q35.dts | 14 #undef PIRQH
18 #define PIRQH 11 macro
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| A D | galileo.dts | 107 PCI_BDF(0, 20, 3) INTD PIRQH
111 PCI_BDF(0, 20, 7) INTD PIRQH
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| A D | cougarcanyon2.dts | 121 PIRQH 11
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| /arch/x86/cpu/queensbay/ |
| A D | tnc.c | 129 writew(PIRQH, &rcba->d31ir); in tnc_irq_init()
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| /arch/x86/cpu/ivybridge/ |
| A D | sdram.c | 388 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); in rcba_config()
391 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR)); in rcba_config()
392 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR)); in rcba_config()
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| /arch/x86/include/asm/arch-ivybridge/ |
| A D | pch.h | 202 #define PIRQH 7 macro
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| /arch/x86/cpu/quark/ |
| A D | quark.c | 326 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), in quark_irq_init()
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| /arch/x86/ |
| A D | Kconfig | 839 Some newer chipsets offer more than four links, commonly up to PIRQH.
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