Searched refs:PLL (Results 1 – 16 of 16) sorted by relevance
| /arch/arm/mach-davinci/ |
| A D | Kconfig | 53 comment "DA850 PLL Initialization Parameters"
62 int "PLLC0 PLL Post-Divider"
65 Value written to PLLC0 PLL Post-Divider Control Register
110 hex "PLLC1 PLL Post-Divider"
113 Value written to PLLC1 PLL Post-Divider Control Register
|
| /arch/powerpc/cpu/mpc83xx/hrcw/ |
| A D | Kconfig | 30 prompt "System PLL VCO division"
52 prompt "System PLL multiplication factor"
112 bool "Core PLL bypassed"
117 prompt "Core PLL Ratio"
137 prompt "Core PLL VCO Divider"
155 prompt "QUICC Engine PLL VCO Divider"
166 prompt "QUICC Engine PLL division factor"
177 prompt "QUICC Engine PLL multiplication factor"
|
| /arch/arm/mach-sc5xx/ |
| A D | Kconfig | 272 Select 0 to pass CLKIN to PLL
273 Select 1 to pass CLKIN/2 to PLL
350 bool "DDRCLK From 3rd PLL"
353 3rd PLL output is connected to DMC block when set.
361 PLL multiplier value for the 3rd PLL.
369 PLL divider value for the 3rd PLL.
376 Select 0 to pass CLKIN to PLL
377 Select 1 to pass CLKIN/2 to PLL
|
| /arch/powerpc/cpu/mpc83xx/initreg/ |
| A D | Kconfig.lcrr | 12 bool "PLL enabled"
15 bool "PLL bypassed"
|
| /arch/arm/mach-socfpga/ |
| A D | qts-filter.sh | 107 * Altera SoCFPGA Clock and PLL configuration
|
| /arch/arm/include/asm/arch-rockchip/ |
| A D | clock.h | 56 #define PLL(_type, _id, _con, _mode, _mshift, \ macro
|
| /arch/powerpc/cpu/mpc8xx/ |
| A D | Kconfig | 118 PLL, Low-Power, and Reset Control Register (15-30)
|
| /arch/arm/cpu/armv8/fsl-layerscape/ |
| A D | Kconfig | 535 This number is the reference clock frequency of core PLL.
536 For most platforms, the core PLL and Platform PLL have the same
549 Platform PLL, in another word:
|
| /arch/arm/dts/ |
| A D | armada-370-xp.dtsi | 308 /* 2 GHz fixed main PLL */
|
| A D | imx8mq-cm.dts | 87 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
|
| A D | armada-375.dtsi | 68 /* 2 GHz fixed main PLL */
|
| A D | armada-38x.dtsi | 696 /* 1 GHz fixed main PLL */
|
| A D | imx8mm-data-modul-edm-sbc.dts | 923 /* Input into codec PLL */
|
| A D | sun9i-a80.dtsi | 167 * would also throw all the PLL clock rates off, or just the
|
| /arch/arm/mach-omap2/am33xx/ |
| A D | Kconfig | 189 The CDCE913 and CDCEL913 devices are modular PLL-based, low cost,
|
| /arch/arm/mach-mvebu/ |
| A D | Kconfig | 63 # Armada PLL frequency (used for NAND clock generation)
|
Completed in 32 milliseconds