1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@amd.com> 5 */ 6 7 #ifndef _ASM_ARCH_HARDWARE_H 8 #define _ASM_ARCH_HARDWARE_H 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 15 #define ZYNQMP_TCM_SIZE 0x40000 16 17 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 18 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 19 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 20 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 21 22 #define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0xFFA50800 23 #define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \ 24 + 0x00000114) 25 #define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210 26 27 #define ADMA_CH0_BASEADDR 0xFFA80000 28 29 #define PS_MODE0 BIT(0) 30 #define PS_MODE1 BIT(1) 31 #define PS_MODE2 BIT(2) 32 #define PS_MODE3 BIT(3) 33 34 #define RESET_REASON_DEBUG_SYS BIT(6) 35 #define RESET_REASON_SOFT BIT(5) 36 #define RESET_REASON_SRST BIT(4) 37 #define RESET_REASON_PSONLY BIT(3) 38 #define RESET_REASON_PMU BIT(2) 39 #define RESET_REASON_INTERNAL BIT(1) 40 #define RESET_REASON_EXTERNAL BIT(0) 41 42 #define CRLAPB_DBG_LPD_CTRL_SETUP_CLK 0x01002002 43 #define CRLAPB_RST_LPD_DBG_RESET 0 44 45 #define CRL_APB_SOFT_RESET_CTRL_MASK 0x10 46 47 struct crlapb_regs { 48 u32 reserved0[36]; 49 u32 cpu_r5_ctrl; /* 0x90 */ 50 u32 reserved1[7]; 51 u32 dbg_lpd_ctrl; /* 0xB0 */ 52 u32 reserved2[29]; 53 u32 timestamp_ref_ctrl; /* 0x128 */ 54 u32 reserved3[53]; 55 u32 boot_mode; /* 0x200 */ 56 u32 reserved4_0[5]; 57 u32 soft_reset; /* 0x218 */ 58 u32 reserved4_10; 59 u32 reset_reason; /* 0x220 */ 60 u32 reserved4_1[6]; 61 u32 rst_lpd_top; /* 0x23C */ 62 u32 rst_lpd_dbg; /* 0x240 */ 63 u32 reserved5[3]; 64 u32 boot_pin_ctrl; /* 0x250 */ 65 u32 reserved6[21]; 66 }; 67 68 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 69 70 #define ZYNQMP_IOU_SECURE_SLCR 0xFF240000 71 72 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 73 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 74 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 75 76 struct iou_scntr_secure { 77 u32 counter_control_register; 78 u32 reserved0[7]; 79 u32 base_frequency_id_register; 80 }; 81 82 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 83 84 #define ZYNQMP_PS_VERSION 0xFFCA0044 85 #define ZYNQMP_PS_VER_MASK GENMASK(1, 0) 86 87 /* Bootmode setting values */ 88 #define BOOT_MODES_MASK 0x0000000F 89 #define QSPI_MODE_24BIT 0x00000001 90 #define QSPI_MODE_32BIT 0x00000002 91 #define SD_MODE 0x00000003 /* sd 0 */ 92 #define SD_MODE1 0x00000005 /* sd 1 */ 93 #define NAND_MODE 0x00000004 94 #define EMMC_MODE 0x00000006 95 #define USB_MODE 0x00000007 96 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 97 #define JTAG_MODE 0x00000000 98 #define BOOT_MODE_USE_ALT 0x100 99 #define BOOT_MODE_ALT_SHIFT 12 100 /* SW secondary boot modes 0xa - 0xd */ 101 #define SW_USBHOST_MODE 0x0000000A 102 #define SW_SATA_MODE 0x0000000B 103 104 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 105 106 struct iou_slcr_regs { 107 u32 mio_pin[78]; 108 u32 reserved[442]; 109 }; 110 111 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 112 113 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 114 115 struct rpu_regs { 116 u32 rpu_glbl_ctrl; 117 u32 reserved0[63]; 118 u32 rpu0_cfg; /* 0x100 */ 119 u32 reserved1[63]; 120 u32 rpu1_cfg; /* 0x200 */ 121 }; 122 123 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 124 125 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 126 127 struct crfapb_regs { 128 u32 reserved0[65]; 129 u32 rst_fpd_apu; /* 0x104 */ 130 u32 reserved1; 131 }; 132 133 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 134 135 #define ZYNQMP_CCI_REG_CCI_MISC_CTRL 0xFD5E0040 136 #define ZYNQMP_CCI_REG_CCI_MISC_CTRL_NIDEN BIT(1) 137 138 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 139 140 struct apu_regs { 141 u32 reserved0[16]; 142 u32 rvbar_addr0_l; /* 0x40 */ 143 u32 rvbar_addr0_h; /* 0x44 */ 144 u32 reserved1[20]; 145 }; 146 147 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 148 149 /* Board version value */ 150 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 151 #define ZYNQMP_CSU_VERSION_SILICON 0x0 152 #define ZYNQMP_CSU_VERSION_QEMU 0x3 153 154 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 155 156 #define ZYNQMP_SILICON_VER_MASK 0xF 157 #define ZYNQMP_SILICON_VER_SHIFT 0 158 159 #define CSU_JTAG_SEC_GATE_DISABLE GENMASK(7, 0) 160 #define CSU_JTAG_DAP_ENABLE_DEBUG GENMASK(7, 0) 161 #define CSU_JTAG_CHAIN_WR_SETUP GENMASK(1, 0) 162 #define CSU_PCAP_PROG_RELEASE_PL BIT(0) 163 164 #define ZYNQMP_CSU_STATUS_AUTHENTICATED BIT(0) 165 #define ZYNQMP_CSU_STATUS_ENCRYPTED BIT(1) 166 167 struct csu_regs { 168 u32 status; 169 u32 reserved0[3]; 170 u32 multi_boot; 171 u32 reserved1[7]; 172 u32 jtag_chain_status_wr; 173 u32 jtag_chain_status; 174 u32 jtag_sec; 175 u32 jtag_dap_cfg; 176 u32 idcode; 177 u32 version; 178 u32 reserved2[3054]; 179 u32 pcap_prog; 180 }; 181 182 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 183 184 #define ZYNQMP_PMU_BASEADDR 0xFFD80000 185 186 struct pmu_regs { 187 u32 reserved0[16]; 188 u32 gen_storage4; /* 0x40 */ 189 u32 reserved1[1]; 190 u32 gen_storage6; /* 0x48 */ 191 u32 reserved2[3]; 192 u32 pers_gen_storage2; /* 0x58 */ 193 }; 194 195 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) 196 197 #endif /* _ASM_ARCH_HARDWARE_H */ 198