1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> 4 */ 5 6 #ifndef __MESON_SM_H__ 7 #define __MESON_SM_H__ 8 9 #include <asm/types.h> 10 11 /** 12 * meson_sm_read_efuse - read efuse memory into buffer 13 * 14 * @offset: offset from the start efuse memory 15 * @buffer: pointer to buffer 16 * @size: number of bytes to read 17 * @return: number of bytes read 18 */ 19 ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size); 20 21 /** 22 * meson_sm_write_efuse - write into efuse memory from buffer 23 * 24 * @offset: offset from the start efuse memory 25 * @buffer: pointer to buffer 26 * @size: number of bytes to write 27 * @return: number of bytes written 28 */ 29 ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size); 30 31 #define SM_SERIAL_SIZE 12 32 #define MESON_CPU_ID_SZ 4 33 #define MESON_CHIP_ID_SZ 16 34 35 /** 36 * union meson_cpu_id - Amlogic cpu_id. 37 * @raw: buffer to hold the cpu_id value as sequential bytes. 38 * @val: cpu_id represented as 32 bit value. 39 */ 40 union meson_cpu_id { 41 u8 raw[MESON_CPU_ID_SZ]; 42 u32 val; 43 }; 44 45 /** 46 * struct meson_sm_chip_id - Amlogic chip_id. 47 * @cpu_id: cpu_id value, which is distinct from socinfo in that the order of 48 * PACK & MINOR bytes are swapped according to Amlogic chip_id format. 49 * @serial: 12 byte unique SoC number, identifying particular die, read 50 * usually from efuse OTP storage. Serial comes in little-endian 51 * order. 52 */ 53 struct meson_sm_chip_id { 54 union meson_cpu_id cpu_id; 55 u8 serial[SM_SERIAL_SIZE]; 56 }; 57 58 /** 59 * meson_sm_get_serial - read chip unique serial (OTP data) into buffer 60 * 61 * @buffer: pointer to buffer 62 * @size: buffer size. 63 * 64 * Serial is returned in big-endian order. 65 * 66 * @return: zero on success or -errno on failure 67 */ 68 int meson_sm_get_serial(void *buffer, size_t size); 69 70 /** 71 * meson_sm_get_chip_id - read Amlogic chip_id 72 * 73 * @chip_id: pointer to buffer capable to hold the struct meson_sm_chip_id 74 * 75 * Amlogic SoCs support 2 versions of chip_id. Function requests the newest 76 * one (v2), but if chip_id v2 is not supported, then secure monitor returns 77 * v1. All differences between v1 and v2 versions are handled by this function 78 * and chip_id is returned in unified format. 79 * 80 * chip_id contains serial, which is returned here in little-endian order. 81 * 82 * @return: 0 on success or -errno on failure 83 */ 84 int meson_sm_get_chip_id(struct meson_sm_chip_id *chip_id); 85 86 enum { 87 REBOOT_REASON_COLD = 0, 88 REBOOT_REASON_NORMAL = 1, 89 REBOOT_REASON_RECOVERY = 2, 90 REBOOT_REASON_UPDATE = 3, 91 REBOOT_REASON_FASTBOOT = 4, 92 REBOOT_REASON_SUSPEND_OFF = 5, 93 REBOOT_REASON_HIBERNATE = 6, 94 REBOOT_REASON_BOOTLOADER = 7, 95 REBOOT_REASON_SHUTDOWN_REBOOT = 8, 96 REBOOT_REASON_RPMBP = 9, 97 REBOOT_REASON_CRASH_DUMP = 11, 98 REBOOT_REASON_KERNEL_PANIC = 12, 99 REBOOT_REASON_WATCHDOG_REBOOT = 13, 100 }; 101 102 /** 103 * meson_sm_get_reboot_reason - get reboot reason 104 */ 105 int meson_sm_get_reboot_reason(void); 106 107 #define PWRDM_OFF 0 108 #define PWRDM_ON 1 109 110 /** 111 * meson_sm_pwrdm_set - do command at specified power domain. 112 * 113 * @index: power domain index. 114 * @cmd: command index. 115 * @return: zero on success or error code on failure. 116 */ 117 int meson_sm_pwrdm_set(size_t index, int cmd); 118 119 /** 120 * meson_sm_pwrdm_off - disable specified power domain. 121 * 122 * @index: power domain index. 123 * @return: zero on success or error code on failure. 124 */ 125 #define meson_sm_pwrdm_off(index) \ 126 meson_sm_pwrdm_set(index, PWRDM_OFF) 127 128 /** 129 * meson_sm_pwrdm_on - enable specified power domain. 130 * 131 * @index: power domain index. 132 * @return: zero on success or error code on failure. 133 */ 134 #define meson_sm_pwrdm_on(index) \ 135 meson_sm_pwrdm_set(index, PWRDM_ON) 136 137 #endif /* __MESON_SM_H__ */ 138