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Searched refs:RIFSC_RISC_SEMWL_MASK (Results 1 – 1 of 1) sorted by relevance

/arch/arm/mach-stm32mp/stm32mp2/
A Drifsc.c28 #define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16) macro
169 if (!(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { in rifsc_check_access()
232 (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { in stm32_rifsc_child_pre_probe()
260 (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { in stm32_rifsc_child_post_remove()

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