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Searched refs:RL (Results 1 – 6 of 6) sorted by relevance

/arch/arm/mach-omap2/omap5/
A Demif.c26 .RL = 8,
A Dsdram.c614 .RL = 8,
/arch/arm/mach-omap2/
A Demif-common.c655 u8 RL) in get_sdram_config_reg() argument
665 config_reg |= RL << EMIF_REG_CL_SHIFT; in get_sdram_config_reg()
854 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) in get_ddr_phy_ctrl_1() argument
858 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; in get_ddr_phy_ctrl_1()
/arch/arm/include/asm/arch-mx5/
A Dimx-regs.h180 #define RL(x) (((x) & 0x3) << 8) macro
/arch/arm/include/asm/
A Demif.h1137 u8 RL; member
/arch/arm/mach-mvebu/
A DKconfig260 failure, RL, WL errors and other algorithm failure. At level 1,

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