Searched refs:STM32_DDRCTRL_BASE (Results 1 – 2 of 2) sorted by relevance
| /arch/arm/mach-stm32mp/stm32mp1/ |
| A D | psci.c | 417 clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_HWLPCTL, in ddr_sr_mode_ssr()
421 clrsetbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRTMG, in ddr_sr_mode_ssr()
432 clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, in ddr_sr_mode_ssr()
436 clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, in ddr_sr_mode_ssr()
456 clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, in ddr_sw_self_refresh_in()
458 clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, in ddr_sw_self_refresh_in()
483 ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT, in ddr_sw_self_refresh_in()
562 clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, in ddr_sw_self_refresh_in()
566 setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, in ddr_sw_self_refresh_in()
568 setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, in ddr_sw_self_refresh_in()
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| /arch/arm/mach-stm32mp/include/mach/ |
| A D | stm32.h | 84 #define STM32_DDRCTRL_BASE 0x5A003000 macro
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