Searched refs:STM32_DDRPHYC_BASE (Results 1 – 2 of 2) sorted by relevance
495 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, in ddr_sw_self_refresh_in()499 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, in ddr_sw_self_refresh_in()503 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, in ddr_sw_self_refresh_in()510 setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); in ddr_sw_self_refresh_in()514 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, in ddr_sw_self_refresh_in()520 clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, in ddr_sw_self_refresh_in()528 clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE); in ddr_sw_self_refresh_in()603 clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, in ddr_sw_self_refresh_exit()629 STM32_DDRPHYC_BASE + DDRPHYC_PIR); in ddr_sw_self_refresh_exit()635 ret = secure_waitbits(STM32_DDRPHYC_BASE + DDRPHYC_PGSR, in ddr_sw_self_refresh_exit()[all …]
85 #define STM32_DDRPHYC_BASE 0x5A004000 macro
Completed in 6 milliseconds