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Searched refs:STM32_DDR_BASE (Results 1 – 6 of 6) sorted by relevance

/arch/arm/mach-stm32mp/stm32mp2/
A Darm64-mmu.c12 #if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
13 (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
59 .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
/arch/arm/mach-stm32mp/stm32mp1/
A Dspl.c121 const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1); in stm32_init_tzc_for_optee()
137 .base = STM32_DDR_BASE, in stm32_init_tzc_for_optee()
224 mmu_set_region_dcache_behaviour(STM32_DDR_BASE, in board_init_f()
A Dcpu.c76 start = STM32_DDR_BASE; in dram_bank_mmu_setup()
/arch/arm/mach-stm32mp/
A Dboot_params.c27 if (nt_fw_dtb < STM32_DDR_BASE || in board_fdt_blob_setup()
A DKconfig152 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
/arch/arm/mach-stm32mp/include/mach/
A Dstm32.h121 #define STM32_DDR_BASE 0xC0000000 macro
184 #define STM32_DDR_BASE 0x80000000 macro

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