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Searched refs:STM32_RCC_BASE (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-stm32mp/stm32mp1/
A Dpsci.c159 #define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
406 setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, in ddr_sr_mode_ssr()
413 clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, in ddr_sr_mode_ssr()
554 clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, in ddr_sw_self_refresh_in()
579 setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, in ddr_sw_self_refresh_exit()
736 saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); in psci_system_suspend()
737 saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR); in psci_system_suspend()
744 writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR); in psci_system_suspend()
798 writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR); in psci_system_suspend()
803 writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR); in psci_system_suspend()
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A Dstm32mp13x.c23 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
24 #define RCC_BDCR (STM32_RCC_BASE + 0x400)
25 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x468)
26 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x740)
27 #define RCC_MP_AHB6ENSETR (STM32_RCC_BASE + 0x780)
A Dstm32mp15x.c19 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
20 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
21 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
22 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
23 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
/arch/arm/mach-stm32mp/include/mach/
A Dstm32.h78 #define STM32_RCC_BASE 0x50000000 macro
178 #define STM32_RCC_BASE 0x44200000 macro

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