Searched refs:SUNXI_DRAM_COM_BASE (Results 1 – 15 of 15) sorted by relevance
20 #define SUNXI_DRAM_COM_BASE 0x04002000 macro29 #define SUNXI_DRAM_COM_BASE 0x047FA000 macro33 #define SUNXI_DRAM_COM_BASE 0x04810000 macro
25 #define SUNXI_DRAM_COM_BASE 0x03120000 macro
172 #define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800)173 #define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x)174 #define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x)
36 #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) macro
119 #define SUNXI_DRAM_COM_BASE 0x01c62000 macro
93 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()115 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()140 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_v3s()163 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_a64()190 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h5()218 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_r40()388 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()479 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()828 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
36 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()207 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()302 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()331 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
110 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()132 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority()161 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()293 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_com_init()423 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()602 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
106 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()266 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_com_init()297 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_port_cfg()332 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
35 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()263 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()428 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
204 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()341 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_com_init()826 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in DRAMC_get_dram_size()857 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
96 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_init()270 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
44 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()66 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority()99 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()908 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_phy_init()1204 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_ctrl_init()1215 writel(1, SUNXI_DRAM_COM_BASE + 0x50); in mctl_ctrl_init()
342 void *const mctl_com = (void *)SUNXI_DRAM_COM_BASE; in mctl_com_init()523 void *const mctl_com = (void *)SUNXI_DRAM_COM_BASE; in mctl_phy_init()703 void *const mctl_com = (void *)SUNXI_DRAM_COM_BASE; in mctl_dfi_init()
922 void * const mctl_com = (void *)SUNXI_DRAM_COM_BASE; in mctl_phy_init()1296 void * const mctl_com = (void *)SUNXI_DRAM_COM_BASE; in mctl_ctrl_init()
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