Searched refs:SYSCTL_GPIOMODE_REG (Results 1 – 5 of 5) sorted by relevance
| /arch/mips/mach-mtmips/mt7620/ |
| A D | serial.c | 17 clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M, in board_debug_uart_init()
20 clrbits_32(base + SYSCTL_GPIOMODE_REG, UARTL_GPIO_MODE); in board_debug_uart_init()
30 clrbits_32(base + SYSCTL_GPIOMODE_REG, UARTL_GPIO_MODE); in mtmips_spl_serial_init()
32 clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M, in mtmips_spl_serial_init()
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| A D | mt7620.h | 94 #define SYSCTL_GPIOMODE_REG 0x60 macro
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| /arch/mips/mach-mtmips/mt7621/ |
| A D | serial.c | 17 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE); in board_debug_uart_init()
19 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M); in board_debug_uart_init()
21 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M); in board_debug_uart_init()
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| A D | mt7621.h | 91 #define SYSCTL_GPIOMODE_REG 0x60 macro
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| /arch/mips/mach-mtmips/mt7621/spl/ |
| A D | serial.c | 17 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE); in mtmips_spl_serial_init()
19 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M); in mtmips_spl_serial_init()
21 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M); in mtmips_spl_serial_init()
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