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Searched refs:SYSCTL_GPIO_MODE1_REG (Results 1 – 2 of 2) sorted by relevance

/arch/mips/mach-mtmips/mt7628/
A Dserial.c17 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M); in mtmips_spl_serial_init()
19 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M); in mtmips_spl_serial_init()
23 setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M); in mtmips_spl_serial_init()
24 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M, in mtmips_spl_serial_init()
27 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M); in mtmips_spl_serial_init()
28 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M, in mtmips_spl_serial_init()
A Dmt7628.h57 #define SYSCTL_GPIO_MODE1_REG 0x60 macro

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