SYSCTL_SYSCFG0_REG (reference) in projects: arch

Searched refs:SYSCTL_SYSCFG0_REG (Results 1 – 8 of 8) sorted by relevance

/arch/mips/mach-mtmips/mt7628/
A D	init.c	`26 bs = readl(sysc + SYSCTL_SYSCFG0_REG); in set_init_timer_freq() 63 val = readl(sysc + SYSCTL_SYSCFG0_REG); in print_cpuinfo()`
A D	mt7628.h	`32 #define SYSCTL_SYSCFG0_REG 0x10 macro`
A D	ddr.c	`137 ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE; in mt7628_ddr_init()`
/arch/mips/mach-mtmips/mt7620/
A D	init.c	`92 val = readl(sysc + SYSCTL_SYSCFG0_REG); in mt7620_get_clks() 158 val = readl(sysc + SYSCTL_SYSCFG0_REG); in print_cpuinfo()`
A D	mt7620.h	`31 #define SYSCTL_SYSCFG0_REG 0x10 macro`
A D	dram.c	`75 ddr_type = (readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE_M) in mt7620_dram_init()`
/arch/mips/mach-mtmips/mt7621/
A D	init.c	`44 val = readl(sysc + SYSCTL_SYSCFG0_REG); in print_cpuinfo() 92 bs = readl(sysc + SYSCTL_SYSCFG0_REG); in get_xtal_mhz()`
A D	mt7621.h	`66 #define SYSCTL_SYSCFG0_REG 0x10 macro`

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